Patents by Inventor Hormuzd M. Khosravi

Hormuzd M. Khosravi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100306399
    Abstract: A method and apparatus for traversing a firewall between an Intranet and the Internet without the use of a proxy server is provided. Internet Small Computer Systems Interface (iSCSI) streaming over a firewall is provided by tunneling iSCSI over Hypertext Transport Protocol (Security) (HTTP(S)).
    Type: Application
    Filed: May 26, 2009
    Publication date: December 2, 2010
    Inventors: Hormuzd M. Khosravi, Yasser Rasheed
  • Publication number: 20100306177
    Abstract: An embodiment may include circuitry that may be comprised in a host that may execute an operating system and/or in a server. The circuitry may generate, at least in part, and/or receive, at least in part, at least one request to initiate, at least in part, at least one operation at the host. The least one operation may facilitate, at least in part, examination remotely from the host of information stored at the host. The at least one operation may be performed independently from the operating system and also may be performed at least in part by the circuitry. The examination may facilitate, at least in part, remotely from the host, backup, recovery, and/or determination of corruption of mass storage data stored at the host. Of course, many variations, modifications, and alternatives are possible without departing from this embodiment.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 2, 2010
    Inventors: Hormuzd M. Khosravi, Yasser Rasheed, Dominic Fulginiti, Tim Abels, Divya Naidu Kolar Sunder, Sudheer Mogilappagari
  • Publication number: 20100262739
    Abstract: Embodiments of apparatuses, articles, methods, and systems for associating identifiers with memory locations for controlling memory accesses are generally described herein. Other embodiments may be described and claimed.
    Type: Application
    Filed: June 25, 2010
    Publication date: October 14, 2010
    Inventors: David Durham, Ravi Sahita, Uday R. Savagaonkar, Priya Rajagopal, Hormuzd M. Khosravi
  • Publication number: 20100250797
    Abstract: A platform to support verification of the contents of an input-output device. The platform includes a platform hardware, which may verify the contents of the I/O device. The platform hardware may comprise components such as manageability engine and verification engine that are used to verify the contents of the I/O device even before the contents of the I/O device are exposed to an operating system supported by a host. The platform components may delete the infected portions of the contents of I/O device if the verification process indicates that the contents of the I/O device include the infected portions.
    Type: Application
    Filed: March 31, 2009
    Publication date: September 30, 2010
    Inventors: Hormuzd M. Khosravi, Venkat R. Gokulrangan, Yasser Rasheed, Men Long
  • Patent number: 7805512
    Abstract: A device capable of remote configuration, provisioning and/or updating comprising a network detector capable of detecting a network regardless of the state of the operating system on the device, wherein the network requires layer two authentication, and an Embedded Trust Agent capable of generating an authentication credential for layer two authentication and communicating the authentication credential via a layer two authentication protocol without a functioning operating system.
    Type: Grant
    Filed: December 29, 2007
    Date of Patent: September 28, 2010
    Assignee: Intel Corporation
    Inventor: Hormuzd M. Khosravi
  • Patent number: 7761674
    Abstract: Embodiments of apparatuses, articles, methods, and systems for associating identifiers with memory locations for controlling memory accesses are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: July 20, 2010
    Assignee: Intel Corporation
    Inventors: David Durham, Ravi Sahita, Uday R. Savagaonkar, Priya Rajagopal, Hormuzd M. Khosravi
  • Publication number: 20100169967
    Abstract: In some embodiments, a processor-based system may include at least one processor, at least one memory coupled to the at least one processor, a code block, and code which is executable by the processor-based system to cause the processor-based system to generate integrity information for the code block upon a restart of the processor-based system, securely store the integrity information, and validate the integrity of the code block during a runtime of the processor-based system using the securely stored integrity information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Inventors: Hormuzd M. Khosravi, Vincent J. Zimmer, Divya Naidu Kolar Sunder
  • Publication number: 20100161926
    Abstract: A device, method, and system are disclosed. In one embodiment the device includes logic to handle and protect data. Specifically, the device includes logic to segment data that can receive a data object that needs to be stored. The logic within the device can segment the data object into a plurality of data segments. A segmented portion of the data object is an incomprehensible portion the data object when viewed in the segmented format. The device can then send each of the data segments to a several different storage locations.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 24, 2010
    Inventors: Hong Li, Hormuzd M. Khosravi
  • Publication number: 20100083381
    Abstract: A device, system, and method are disclosed. In an embodiment, the device includes a storage medium to store files. The device also includes a manageability engine. The manageability engine accesses a virus signature file. The manageability engine then performs an anti-virus scan using patterns in the signature file to compare to one or more of the files. The manageability engine then reports the results of the scan to an external agent.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Hormuzd M. Khosravi, Divya Naidu Kolar Sunder, Samuel O. Moffatt, Dominic Fulginiti
  • Patent number: 7646759
    Abstract: A method and apparatus for configuring data plane behavior on network forwarding elements are described. In one embodiment, the method includes receiving, within a network element control plane, protocol configuration information extracted from a protocol application utilizing a network protocol application programming interface (API). Once the protocol configuration information is received, the protocol configuration information is processed using a control interface corresponding to the network protocol implemented by the protocol application. Once the protocol configuration information is processed, the control interface programs one or more data plane forwarding elements of the network element according to protocol configuration information. Accordingly, by providing similar control interfaces for multiple, network protocols, inter-operability between components from multiple vendors is enabled.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: January 12, 2010
    Assignee: Intel Corporation
    Inventors: Shriharsha S. Hegde, Russell J. Fenger, Amol Kulkarni, Hsin-Yuo Liu, Hormuzd M. Khosravi, Manasi Deval
  • Publication number: 20090328042
    Abstract: Methods and systems to detect virtualization of computer system resources, such as by malware, include methods and systems to evaluate information corresponding to a computer processor operating environment, outside of or secure from the operating environment, which may include one or more of a system management mode of operation and a management controller system. Information may include processor register values. Information may be obtained from within the operating environment, such as with a host application running within the operating environment. Information may be obtained outside of the operating environment, such as from a system state map. Information obtained from within the operating environment may be compared to corresponding information obtained outside of the operating environment. Direct memory address (DMA) translation information may be used to determine whether an operating environment is remapping DMA accesses.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Hormuzd M. Khosravi, David Durham
  • Patent number: 7571298
    Abstract: Systems and methods are described herein to provide for host virtual memory reconstitution. Virtual memory reconstitution is the ability to translate the host device's virtual memory addresses to the host device's physical memory addresses. The virtual memory reconstitution methods are independent of the operating system running on the host device.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: August 4, 2009
    Assignee: Intel Corporation
    Inventors: Hormuzd M. Khosravi, David M. Durham, Travis Schluessler, Ravi Sahita, Uday Savagaonkar, Priya Rajagopal
  • Publication number: 20090158409
    Abstract: A device capable of remote configuration, provisioning and/or updating comprising a network detector capable of detecting a network regardless of the state of the operating system on the device, wherein the network requires layer two authentication, and an Embedded Trust Agent capable of generating an authentication credential for layer two authentication and communicating the authentication credential via a layer two authentication protocol without a functioning operating system.
    Type: Application
    Filed: December 29, 2007
    Publication date: June 18, 2009
    Inventor: Hormuzd M. Khosravi
  • Patent number: 7467285
    Abstract: Provided are a method, system, program and device for maintaining shadow page tables in a sequestered memory region. A first processor executing an application invokes a second processor to create a shadow page table used for address translation for the application in a sequestered memory region non-alterable by processes controlled by an operating system executed by the first processor. The shadow page table references at least one page in an operating system memory region accessible to processes controlled by the operating system.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Hormuzd M. Khosravi, Uday Savagaonkar, Ravi Sahita, Priya Rajagopal
  • Publication number: 20080244758
    Abstract: An apparatus to protect one or more hardware devices from unauthorized software access is described herein and comprises, in one embodiment, a virtual machine manager, a memory protection module and an integrity measurement manager. In a further embodiment, a method of providing secure access to one or more hardware devices may include, modifying a page table, verifying the integrity of a device driver, and providing memory protection to the device driver if the device driver is verified.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Ravi Sahita, Hormuzd M. Khosravi, Uday Savagaonkar, David M. Durham
  • Publication number: 20080244725
    Abstract: According to one example embodiment of the inventive subject matter, there is described herein a method and apparatus for securely and efficiently managing packet buffers between protection domains on an Intra-partitioned system using packet queues and triggers. According to one embodiment described in more detail below, there is provided a method and apparatus for optimally transferring packet data across contexts (protected and unprotected) in a commodity operating system.
    Type: Application
    Filed: March 31, 2007
    Publication date: October 2, 2008
    Inventors: Prashant Dewan, Uday Savagaonkar, Hormuzd M. Khosravi
  • Patent number: 7428219
    Abstract: A network element comprises a control element (CE), a plurality of forwarding element (FEs) and an interconnect in communication with said CE and at least one of said FEs. Communication across the interconnect between the CE and the plurality of FEs is done in accordance with a protocol that includes a binding phase used to provide a data channel between the CE and a first one of the FEs. The binding phase is further used to provide a control channel between the CE and the first one of the FEs, the control channel used to transport control and configuration messages. The control channel is separate from the data channel. The protocol also includes a capability discovery phase, a configuration operation phase and an unbind phase executed between the CE and the FE.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: September 23, 2008
    Assignee: Intel Corporation
    Inventor: Hormuzd M. Khosravi
  • Patent number: 7363473
    Abstract: Disclosed is a network processor configured to provide for dynamic service provisioning. A global connector defines a topology of packet processing functions that can be dynamically ordered to provide varying functionality. The global connector may be configured before or during the operation of the network processor. Such a system allows a network processor to provide additional functionality in a relatively easy manner, without necessitating changes to the packet processing functions themselves. Such dynamic service provisioning may include dynamic topology changes, which allows a network processor to reconfigure the structure or operation of multiple processing elements of the processor.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: April 22, 2008
    Assignee: Intel Corporation
    Inventors: Hormuzd M. Khosravi, Bernie Keany
  • Publication number: 20080083030
    Abstract: Methods and apparatuses enable in-memory patching of a program loaded in volatile memory. A service processor identifies a program to be patched and an associated patch for the program. The patch is loaded into memory, including applying relocation fix-ups to the patch. The service processor directs the program to the patch in place of the segment of the program to be patched. The program implements the patch while maintaining program state, and without suspending execution of the program.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: David M. Durham, Hormuzd M. Khosravi, Travis Schluessler, Ravi Sahita, Uday R. Savagaonkar
  • Publication number: 20080077767
    Abstract: Embodiments described herein disclose a method and apparatus for secure page swapping in a virtual memory system. An integrity check value mechanism is used to protect software programs from run-time attacks against memory pages while those pages are swapped to secondary memory. A hash value is computed for an agent page as it is swapped from primary memory to secondary memory. When the page is swapped back into primary memory from secondary memory, that hash value is recomputed to verify that the page was not modified while stored in secondary memory. Alternatively, the hash value is pre-computed and placed in an integrity manifest wherein it is retrieved and verified when the page is loaded back into primary memory from secondary memory.
    Type: Application
    Filed: September 27, 2006
    Publication date: March 27, 2008
    Inventors: Hormuzd M. Khosravi, Uday Savagaonkar, Ravi Sahita, David Durham, Travis Schluessler, Gayathri Nagabhushan