Patents by Inventor Horng-Chih Lin
Horng-Chih Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11257845Abstract: A radio frequency integrated circuit includes a silicon CMOS substrate with at least one CMOS device buried therein, and at least one thin film transistor formed on the silicon CMOS substrate and functioning as a radio frequency device. The thin film transistor includes a T-shaped gate electrode. A method for the fabricating a radio frequency integrated circuit is also disclosed.Type: GrantFiled: July 27, 2020Date of Patent: February 22, 2022Assignee: National Chiao Tung UniversityInventors: Horng-Chih Lin, Yu-An Huang
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Publication number: 20210375946Abstract: A radio frequency integrated circuit includes a silicon CMOS substrate with at least one CMOS device buried therein, and at least one thin film transistor formed on the silicon CMOS substrate and functioning as a radio frequency device. The thin film transistor includes a T-shaped gate electrode. A method for the fabricating a radio frequency integrated circuit is also disclosed.Type: ApplicationFiled: July 27, 2020Publication date: December 2, 2021Inventors: Horng-Chih Lin, Yu-An Huang
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Patent number: 9653552Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: GrantFiled: July 8, 2016Date of Patent: May 16, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Publication number: 20160322463Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: ApplicationFiled: July 8, 2016Publication date: November 3, 2016Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Patent number: 9406800Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: GrantFiled: December 15, 2015Date of Patent: August 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Publication number: 20160104800Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: ApplicationFiled: December 15, 2015Publication date: April 14, 2016Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Patent number: 9214554Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: GrantFiled: January 28, 2015Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Publication number: 20150206970Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: ApplicationFiled: January 28, 2015Publication date: July 23, 2015Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang-Yu
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Patent number: 8946811Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of said top surface and said two opposed side surfaces, and a gate electrode covering at least a portion of said gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: GrantFiled: July 10, 2006Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Patent number: 8932916Abstract: A method for fabricating a thin-film transistor is disclosed. Firstly, a patterned dielectric mask structure with a bottom thereof having a gate dielectric layer is formed on a gate-stacked structure so that the gate dielectric layer covers a gate of the gate-stacked structure. Top surface of the patterned dielectric mask structure has at least two openings. A semiconductor layer is formed on the gate-stacked structure via the openings by a sputtering method. The semiconductor layer comprises a channel above the gate, a source and a drain below the openings. The channel has a thickness which sequentially decreases from edge to center.Type: GrantFiled: November 8, 2013Date of Patent: January 13, 2015Assignee: National Chiao Tung UniversityInventors: Horng-Chih Lin, Rong-Jhe Lyu
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Publication number: 20140357017Abstract: A method for fabricating a thin-film transistor is disclosed. Firstly, a patterned dielectric mask structure with a bottom thereof having a gate dielectric layer is formed on a gate-stacked structure so that the gate dielectric layer covers a gate of the gate-stacked structure. Top surface of the patterned dielectric mask structure has at least two openings. A semiconductor layer is formed on the gate-stacked structure via the openings by a sputtering method. The semiconductor layer comprises a channel above the gate, a source and a drain below the openings. The channel has a thickness which sequentially decreases from edge to center.Type: ApplicationFiled: November 8, 2013Publication date: December 4, 2014Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: HORNG-CHIH LIN, RONG-JHE LYU
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Patent number: 7977755Abstract: The present invention discloses a suspended nanochannel transistor structure and a method for fabricating the same. The transistor structure of the present invention comprises a substrate; a side gate formed on the substrate; a dielectric layer covering the substrate and the side gate; a suspended nanochannel formed beside the lateral of the side gate with an air gap existing between the suspended nanochannel and the dielectric layer; a source and a drain formed over the dielectric layer and respectively arranged at two ends of the suspended nanochannel. The electrostatic force of the side gate attracts or repels the suspended nanochannel and thus fast varies the equivalent thickness of the side-gate dielectric layer. Thereby, the on/off state of the element is rapidly switched, or the initial voltage of the channel is altered.Type: GrantFiled: December 17, 2008Date of Patent: July 12, 2011Assignee: National Chiao Tung UniversityInventors: Horng-Chih Lin, Chun-Jung Su, Hsing-Hui Hsu, Guan-Jang Li
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Patent number: 7972912Abstract: A method of fabricating a semiconductor device includes first providing an insulation substrate. A patterned conductive layer is formed over the insulation substrate, and the patterned conductive layer includes a channel region and a number of protruding regions. A gate structure layer is formed over the insulation substrate. The gate structure layer covers a part of the patterned conductive layer, and each of the protruding regions has an exposed region. A doping process is performed to dope at least the exposed region of the patterned conductive layer to form a number of S/D regions.Type: GrantFiled: January 13, 2009Date of Patent: July 5, 2011Assignee: Industrial Technology Research InstituteInventors: Huai-Yuan Tseng, Chen-Pang Kung, Horng-Chih Lin, Ming-Hsien Lee
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Patent number: 7723789Abstract: A nonvolatile memory device with nanowire channel and a method for fabricating the same are proposed, in which side etching is used to shrink side walls of a side-gate to form a nanowire pattern, thereby fabricating a nanowire channel on the dielectric of the side walls of the side-gate. A nonvolatile memory device with nanowire channel and dual-gate control can thus be achieved. This nonvolatile memory device can enhance data writing and erasing efficiency, and also has the capability of low voltage operation. Moreover, through a process of low cost and easy steps, highly reproducible and mass producible fabrication of nanowire devices can be accomplished.Type: GrantFiled: February 4, 2008Date of Patent: May 25, 2010Assignee: National Chiao Tung UniversityInventors: Horng-Chih Lin, Chun-Jung Su, Hsin-Hwei Hsu
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Publication number: 20090130804Abstract: A method of fabricating a semiconductor device includes first providing an insulation substrate. A patterned conductive layer is formed over the insulation substrate, and the patterned conductive layer includes a channel region and a number of protruding regions. A gate structure layer is formed over the insulation substrate. The gate structure layer covers a part of the patterned conductive layer, and each of the protruding regions has an exposed region. A doping process is performed to dope at least the exposed region of the patterned conductive layer to form a number of S/D regions.Type: ApplicationFiled: January 13, 2009Publication date: May 21, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Huai-Yuan Tseng, Chen-Pang Kung, Horng-Chih Lin, Ming-Hsien Lee
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Patent number: 7504694Abstract: A structure of semiconductor device including an insulation substrate is provided. A channel layer is disposed on the insulation substrate. A plurality of doped layers is disposed on the insulation substrate, and protrudes from the channel layer. The doped layers form at least two source/drain electrode (S/D electrode) pairs, and each of the S/D electrode pairs has a different extension direction with respect to the channel layer. A gate dielectric layer is disposed on the channel layer. A gate layer is disposed on the gate dielectric layer. Preferably, for example, the extension direction of at least one of the S/D electrode pairs is a first direction, and the extension direction of at least another one of the S/D electrode pairs is a second direction.Type: GrantFiled: September 7, 2006Date of Patent: March 17, 2009Assignee: Industrial Technology Research InstituteInventors: Huai-Yuan Tseng, Chen-Pang Kung, Horng-Chih Lin, Ming-Hsien Lee
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Publication number: 20090065852Abstract: A nonvolatile memory device with nanowire channel and a method for fabricating the same are proposed, in which side etching is used to shrink side walls of a side-gate to form a nanowire pattern, thereby fabricating a nanowire channel on the dielectric of the side walls of the side-gate. A nonvolatile memory device with nanowire channel and dual-gate control can thus be achieved. This nonvolatile memory device can enhance data writing and erasing efficiency, and also has the capability of low voltage operation. Moreover, through a process of low cost and easy steps, highly reproducible and mass producible fabrication of nanowire devices can be accomplished.Type: ApplicationFiled: February 4, 2008Publication date: March 12, 2009Inventors: Horng-Chih LIN, Chun-Jung Su, Hsin-Hwei Hsu
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Publication number: 20080006908Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of said top surface and said two opposed side surfaces, and a gate electrode covering at least a portion of said gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.Type: ApplicationFiled: July 10, 2006Publication date: January 10, 2008Inventors: Hong-Nien Lin, Horng-Chih Lin, Tiao-Yuan Huang
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Publication number: 20070267697Abstract: A structure of semiconductor device including an insulation substrate is provided. A channel layer is disposed on the insulation substrate. A plurality of doped layers is disposed on the insulation substrate, and protrudes from the channel layer. The doped layers form at least two source/drain electrode (S/D electrode) pairs, and each of the S/D electrode pairs has a different extension direction with respect to the channel layer. A gate dielectric layer is disposed on the channel layer. A gate layer is disposed on the gate dielectric layer. Preferably, for example, the extension direction of at least one of the S/D electrode pairs is a first direction, and the extension direction of at least another one of the S/D electrode pairs is a second direction.Type: ApplicationFiled: September 7, 2006Publication date: November 22, 2007Applicant: Industrial Technology Research InstituteInventors: Huai-Yuan Tseng, Chen-Pang Kung, Horng-Chih Lin, Ming-Hsien Lee
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Patent number: 6667508Abstract: A novel structure of nonvolatile memory is formed on p type silicon and includes a stacked gate, a tunneling dielectric layer, a floating gate (FG), a dielectric layer and a control gate (CG). One side of the stacked gate has a source region and the other has a drain region, wherein the surface of the source region includes a thin metal silicide connected with a channel region to form a Schottky barrier. A tilted angle implant with As or P doping is performed on the p type silicon substrate to form a drain region and extend a portion of the drain region to a channel region under the stacked gate. For implanting, an n doped source region is also formed, creating an offset between the source region and the channel region as a result of the tilted angle implant. For programming, the source region is grounded, positive voltage is applied to the drain region and the gate, such that the hot carriers inject into the floating gate through the channel adjacent to the source region.Type: GrantFiled: December 19, 2001Date of Patent: December 23, 2003Inventors: Horng-Chih Lin, Tiao-Yuan Huang