Patents by Inventor Horng-Non Chern

Horng-Non Chern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6150223
    Abstract: A method for forming a different width of gate spacer is disclosed. The method includes firstly forming a gate oxide layer on a semiconductor substrate. A polysilicon layer, a conductive layer, a first dielectric layer are formed in order on the gate oxide layer. The first dielectric layer, the conductive layer, the polysilicon layer, and the gate oxide layer are further etched using them as the interior gate and the peripheral gate. Next, second dielectric layer, third dielectric layer, and fourth dielectric layer are formed over the interior gate and the peripheral gate, and a first photoresist layer abuts the surface of the fourth dielectric layer of the interior circuit. Moreover, etching the fourth dielectric layer of peripheral gate to form a second spacer of peripheral gate, and etching the third dielectric layer of the peripheral gate are undertaken to form a first spacer of the peripheral gate.
    Type: Grant
    Filed: April 7, 1999
    Date of Patent: November 21, 2000
    Assignee: United Microelectronics Corp.
    Inventors: Horng-Non Chern, Kun-Chi Lin, Alex Hou, Chien-Hua Tsai, Tsu-An Lin