Patents by Inventor Horng-Sheng Yan
Horng-Sheng Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220398155Abstract: A data rebuilding method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: establishing a connection between the memory storage apparatus and a host system; storing a first data to a memory of the host system via the connection; detecting an error in the first data in the memory; and rebuilding a part of data in the first data in the memory according to the error.Type: ApplicationFiled: July 28, 2021Publication date: December 15, 2022Applicant: PHISON ELECTRONICS CORP.Inventor: Horng-Sheng Yan
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Patent number: 10620874Abstract: A memory management method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first write command and writing data corresponding to the first write command into a first spare physical erasing unit; detecting an amount of second spare physical erasing units excluding the first spare physical erasing unit; determining whether the amount of the second spare physical erasing units is less than a threshold value; and performing a first procedure if the amount of the second spare physical erasing units is less than the threshold value. The first procedure includes: moving valid data in the physical erasing units into at least one third spare physical erasing unit; and adjusting the threshold value from a first threshold value to a second threshold value.Type: GrantFiled: August 17, 2015Date of Patent: April 14, 2020Assignee: PHISON ELECTRONICS CORP.Inventors: Horng-Sheng Yan, Kok-Yong Tan
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Patent number: 10338854Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. In an exemplary embodiment, the memory management method includes: receiving a first write command and first write data and obtaining a first number; programming the first write data and moving first storage data stored in a plurality of first physical programming units, where a total number of the first physical programming units conforms to the first number; receiving a second write command and second write data and obtaining a second number; programming the second write data and moving second storage data stored in a plurality of second physical programming units, where a total number of the second physical programming units conforms to the second number; and erasing at least one physical erasing unit. Accordingly, waste of system resource in the data merging procedure may be reduced.Type: GrantFiled: September 7, 2015Date of Patent: July 2, 2019Assignee: PHISON ELECTRONICS CORP.Inventors: Kok-Yong Tan, Horng-Sheng Yan
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Patent number: 10289334Abstract: A valid data merging method, a memory controller and a memory storage apparatus are provided. The method includes: grouping physical erasing units in a data area to at least a first group and a second group; selecting a first physical erasing unit from the second group; and copying valid data of the first physical erasing unit to a second physical erasing unit. A trim table recording special type data of the physical erasing units of the first group is not stored in a non-volatile rewriteable memory module, and a trim table recording special type data of the physical erasing units of the second group is stored in the non-volatile rewriteable memory module. The valid data does not include the special type data of the first physical erasing unit.Type: GrantFiled: January 4, 2016Date of Patent: May 14, 2019Assignee: PHISON ELECTRONICS CORP.Inventor: Horng-Sheng Yan
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Patent number: 10101914Abstract: A memory management method for a rewritable non-volatile memory module is provided. The memory management method includes receiving an adjust command from a host system, wherein the adjust command is configured to indicate that data stored in at least one logical unit of a plurality of logical units is invalid; updating a logical address status table according to the adjust command, wherein the logical address status table reflects a data status of the data stored in each of the logical units, wherein the data status includes a first state or a second state; and updating a physical address status table according to the logical address status table and the physical address status table if a predetermined condition is met, wherein the physical address status table reflects a data status of data stored in each of a plurality of physical programming units.Type: GrantFiled: April 8, 2016Date of Patent: October 16, 2018Assignee: PHISON ELECTRONICS CORP.Inventors: Kok-Yong Tan, Horng-Sheng Yan
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Publication number: 20170228162Abstract: A memory management method for a rewritable non-volatile memory module is provided. The memory management method includes receiving an adjust command from a host system, wherein the adjust command is configured to indicate that data stored in at least one logical unit of a plurality of logical units is invalid; updating a logical address status table according to the adjust command, wherein the logical address status table reflects a data status of the data stored in each of the logical units, wherein the data status includes a first state or a second state; and updating a physical address status table according to the logical address status table and the physical address status table if a predetermined condition is met, wherein the physical address status table reflects a data status of data stored in each of a plurality of physical programming units.Type: ApplicationFiled: April 8, 2016Publication date: August 10, 2017Inventors: Kok-Yong Tan, Horng-Sheng Yan
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Patent number: 9720609Abstract: A data protecting method for a rewritable non-volatile memory module is provided. The method includes assigning a plurality of physical pages into a plurality of encoding groups to group a first physical page to a first encoding group and group a second physical page to a second encoding group, where each of the physical pages stores user data and a parity code corresponding to the user data, the first physical page is composed of memory cells of a first word line, and the second physical page is composed of memory cells of a second word line adjacent to the first word line. The method also includes respectively encoding the user data in the physical pages of the encoding groups for generating a plurality of group parity codes respectively corresponding to the encoding groups.Type: GrantFiled: May 6, 2016Date of Patent: August 1, 2017Assignee: PHISON ELECTRONICS CORP.Inventors: Horng-Sheng Yan, Kok-Yong Tan
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Publication number: 20170115925Abstract: A valid data merging method, a memory controller and a memory storage apparatus are provided. The method includes: grouping physical erasing units in a data area to at least a first group and a second group; selecting a first physical erasing unit from the second group; and copying valid data of the first physical erasing unit to a second physical erasing unit. A trim table recording special type data of the physical erasing units of the first group is not stored in a non-volatile rewriteable memory module, and a trim table recording special type data of the physical erasing units of the second group is stored in the non-volatile rewriteable memory module. The valid data does not include the special type data of the first physical erasing unit.Type: ApplicationFiled: January 4, 2016Publication date: April 27, 2017Inventor: Horng-Sheng Yan
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Publication number: 20170024136Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. In an exemplary embodiment, the memory management method includes: receiving a first write command and first write data and obtaining a first number; programming the first write data and moving first storage data stored in a plurality of first physical programming units, where a total number of the first physical programming units conforms to the first number; receiving a second write command and second write data and obtaining a second number; programming the second write data and moving second storage data stored in a plurality of second physical programming units, where a total number of the second physical programming units conforms to the second number; and erasing at least one physical erasing unit. Accordingly, waste of system resource in the data merging procedure may be reduced.Type: ApplicationFiled: September 7, 2015Publication date: January 26, 2017Inventors: Kok-Yong Tan, Horng-Sheng Yan
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Publication number: 20170003897Abstract: A memory management method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first write command and writing data corresponding to the first write command into a first spare physical erasing unit; detecting an amount of second spare physical erasing units excluding the first spare physical erasing unit; determining whether the amount of the second spare physical erasing units is less than a threshold value; and performing a first procedure if the amount of the second spare physical erasing units is less than the threshold value. The first procedure includes: moving valid data in the physical erasing units into at least one third spare physical erasing unit; and adjusting the threshold value from a first threshold value to a second threshold value.Type: ApplicationFiled: August 17, 2015Publication date: January 5, 2017Inventors: Horng-Sheng Yan, Kok-Yong Tan
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Patent number: 9229798Abstract: An error handling method, a memory storage device and a memory controlling circuit unit are provided. The method includes obtaining a finished event corresponding to a channel; determining whether the finished event is a failed event, if the finished event is the failed event; stopping an operation of the channel and performing a first update operation on a counting value corresponding to the channel; and if the finished event is not the failed event, keeping the counting value corresponding to the channel unchanged and processing the finished event. The step of the processing the finished event includes performing a second update operation on the counting value corresponding to the channel if the finished event is the failed event, and recovering the operation of the channel if the counting value matches a threshold criterion. Accordingly, it can improve the accessing performance.Type: GrantFiled: April 9, 2014Date of Patent: January 5, 2016Assignee: PHISON ELECTRONICS CORP.Inventor: Horng-Sheng Yan
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Publication number: 20150193291Abstract: An error handling method, a memory storage device and a memory controlling circuit unit are provided. The method includes obtaining a finished event corresponding to a channel; determining whether the finished event is a failed event, if the finished event is the failed event; stopping an operation of the channel and performing a first update operation on a counting value corresponding to the channel; and if the finished event is not the failed event, keeping the counting value corresponding to the channel unchanged and processing the finished event. The step of the processing the finished event includes performing a second update operation on the counting value corresponding to the channel if the finished event is the failed event, and recovering the operation of the channel if the counting value matches a threshold criterion. Accordingly, it can improve the accessing performance.Type: ApplicationFiled: April 9, 2014Publication date: July 9, 2015Applicant: PHISON ELECTRONICS CORP.Inventor: Horng-Sheng Yan
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Patent number: 8074128Abstract: A block management and replacement method for a flash memory is provided. The method includes grouping physical blocks of the flash memory into physical units and dividing the physical units as a usage area and a replacement area, wherein the physical blocks grouped into the same physical unit are accessed by using a multi-planes accessing command. The method also includes when one of the physical block of the physical unit in the usage area is damaged, replacing the physical unit having the damaged physical block with one physical unit selected from the replacement area and recording the undamaged physical block within the replaced physical unit if there is an applicable physical unit in the replacement area; and replacing the damaged physical block with one physical block selected from the replacement area if there is no applicable physical unit but an undamaged physical block in the replacement area.Type: GrantFiled: December 4, 2008Date of Patent: December 6, 2011Assignee: Phison Electronics Corp.Inventors: Chien-Hua Chu, Chih-Kang Yeh, Horng-Sheng Yan
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Publication number: 20100088540Abstract: A block management and replacement method for a flash memory is provided. The method includes grouping physical blocks of the flash memory into physical units and dividing the physical units as a usage area and a replacement area, wherein the physical blocks grouped into the same physical unit are accessed by using a multi-planes accessing command. The method also includes when one of the physical block of the physical unit in the usage area is damaged, replacing the physical unit having the damaged physical block with one physical unit selected from the replacement area and recording the undamaged physical block within the replaced physical unit if there is an applicable physical unit in the replacement area; and replacing the damaged physical block with one physical block selected from the replacement area if there is no applicable physical unit but an undamaged physical block in the replacement area.Type: ApplicationFiled: December 4, 2008Publication date: April 8, 2010Applicant: PHISON ELECTRONICS CORP.Inventors: Chien-Hua Chu, Chih-Kang Yeh, Horng-Sheng Yan