Patents by Inventor Horst Baumeister

Horst Baumeister has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220310777
    Abstract: IC chip package routing structures including a metal-insulator-metal (MIM) capacitor integrated with redistribution layers. An active side of an IC chip may be electrically coupled to the redistribution layers through first-level interconnects. The redistribution layers terminate at interfaces suitable for coupling a package to a host component through second-level interconnects. The MIM capacitor structure may comprise materials suitable for high temperature processing, for example of 350° C., or more. The MIM capacitor structure may therefore be fabricated over a host substrate using higher temperature processing. The redistribution layers and MIM capacitor may then be embedded within package dielectric material(s) using lower temperature processing. An IC chip may be attached to the package routing structure, and the package then separated from the host substrate for further assembly to a host component.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Applicant: Intel Corporation
    Inventors: David O'Sullivan, Georg Seidemann, Bernd Waidhas, Horst Baumeister
  • Patent number: 9793220
    Abstract: A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: October 17, 2017
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventors: Hans-Joachim Barth, Horst Baumeister, Peter Baumgartner, Philipp Riess, Jesenka Veledar Krueger
  • Publication number: 20130240884
    Abstract: A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The capacitance may vary depending upon local environmental conditions such as mechanical stress (e.g., warpage or shear stress), mechanical pressure, temperature, and/or humidity. It may be desirable to provide a capacitor integrated into a semiconductor chip that is sufficiently small and sensitive to accurately measure conditions expected to be experienced by a semiconductor chip.
    Type: Application
    Filed: December 28, 2012
    Publication date: September 19, 2013
    Applicant: Intel Mobile Communications GmbH
    Inventors: Hans-Joachim Barth, Horst Baumeister, Peter Baumgartner, Philipp Riess, Jesenka Veledar Krueger
  • Patent number: 7973547
    Abstract: A method for detecting a crack in a semiconductor wafer, which includes an electrical device and a connecting pad electrically coupled with the electrical device, is described. The crack is detected by an acoustic detector being acoustically coupled to the semiconductor wafer during contacting the contacting pad with a probe.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: July 5, 2011
    Assignee: Infineon Technologies AG
    Inventors: Alois Nitsch, Rainer Tilgner, Horst Baumeister
  • Publication number: 20100039128
    Abstract: A method for detecting a crack in a semiconductor wafer, which includes an electrical device and a connecting pad electrically coupled with the electrical device, is described. The crack is detected by an acoustic detector being acoustically coupled to the semiconductor wafer during contacting the contacting pad with a probe.
    Type: Application
    Filed: August 13, 2008
    Publication date: February 18, 2010
    Inventors: Alois Nitsch, Rainer Tilgner, Horst Baumeister
  • Patent number: 6794209
    Abstract: The invention relates to a method for fabricating a structure in a semiconductor material. At least one etching step is carried out in-situ in an epitaxy installation and tertiary butyl chloride is used as the etchant. The at least one etching step produces at least one grating structure of a DFB laser. This provides an efficient method for fabricating DFB lasers.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: September 21, 2004
    Assignee: Infineon Technologies AG
    Inventors: Horst Baumeister, Roland Gessner, Eberhard Veuhoff, Gundolf Wenger
  • Patent number: 6699778
    Abstract: A method produces structures for semiconductor components, particularly BH laser diodes, in which a mask material is applied to a sample in a masking step. The etch rate in an etching step depends upon the composition and/or nature of the mask material. The etch rate is selected in such a way so that the mask is at least partly dissolved during the etching step. It is therefore possible to easily remove the mask from the semiconductor material and apply additional layers in situ during the fabrication of semiconductor components.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: March 2, 2004
    Assignee: Infineon Technologies AG
    Inventors: Bernd Borchert, Horst Baumeister, Roland Gessner, Eberhard Veuhoff, Gundolf Wenger
  • Patent number: 6599843
    Abstract: Method of producing a structure for III-V semiconductor components in which a mask is applied to a sample in a masking step, characterized in that at least one mask material is a monocrystalline III-V semiconductor material. This makes possible an easy in-situ removal of the mask from the semiconductor material, which in turn makes possible the growing of additional layers.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: July 29, 2003
    Assignee: Infineon Technologies AG
    Inventors: Horst Baumeister, Roland Gessner, Eberhard Veuhoff, Gundolf Wenger
  • Publication number: 20030003615
    Abstract: The invention relates to a method for fabricating a structure in a semiconductor material. At least one etching step is carried out in-situ in an epitaxy installation and tertiary butyl chloride is used as the etchant. The at least one etching step produces at least one grating structure of a DFB laser. This provides an efficient method for fabricating DFB lasers.
    Type: Application
    Filed: July 1, 2002
    Publication date: January 2, 2003
    Inventors: Horst Baumeister, Roland Gessner, Eberhard Veuhoff, Gundolf Wenger
  • Publication number: 20020182873
    Abstract: Method of producing a structure for III-V semiconductor components in which a mask is applied to a sample in a masking step, characterized in that at least one mask material is a monocrystalline III-V semiconductor material. This makes possible an easy in-situ removal of the mask from the semiconductor material, which in turn makes possible the growing of additional layers.
    Type: Application
    Filed: May 29, 2001
    Publication date: December 5, 2002
    Inventors: Horst Baumeister, Roland Gessner, Eberhard Veuhoff, Gundolf Wenger
  • Publication number: 20020182879
    Abstract: A method produces structures for semiconductor components, particularly BH laser diodes, in which a mask material is applied to a sample in a masking step. The etch rate in an etching step depends upon the composition and/or nature of the mask material. The etch rate is selected in such a way so that the mask is at least partly dissolved during the etching step. It is therefore possible to easily remove the mask from the semiconductor material and apply additional layers in situ during the fabrication of semiconductor components.
    Type: Application
    Filed: January 18, 2002
    Publication date: December 5, 2002
    Inventors: Bernd Borchert, Horst Baumeister, Roland Gessner, Eberhard Veuhoff, Gundolf Wenger