Patents by Inventor Horst Gesing

Horst Gesing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Jig
    Patent number: 4036485
    Abstract: A soldering jig made of plastic.
    Type: Grant
    Filed: June 19, 1973
    Date of Patent: July 19, 1977
    Assignee: Licentia Patent-Verwaltungs-G.m.b.H.
    Inventors: Rigobert Schimmer, Horst Gesing, Wolfgang Beerwerth, Jurgen Messerschmidt
  • Device for bonding electrodes to semiconductor devices
    Patent number: 4018373
    Abstract: An electrode centering and clamping device for producing diffused, contacted and surface passivated semiconductor chips for semiconductor devices, wherein after producing a semiconductor wafer with a given arrangement of layers and regions of different conductance and different conductivity types for a plurality of devices by doping with impurity forming elements, both of the major surfaces of the semiconductor wafer are provided with respective metal layers and output electrodes are applied to both of the metal layers for the plurality of devices with the output electrodes being of such a thickness and overlying such areas of the metal layers so that the thickness of the electrodes will still be sufficient for further processing after a subsequent separation of the wafer into the plurality of chips and the major surfaces of the chips after separation, are completely covered by the output electrodes.
    Type: Grant
    Filed: October 31, 1975
    Date of Patent: April 19, 1977
    Assignee: Licentia Patent-Verwaltungs-G.m.b.H.
    Inventors: Wolfgang Beerwerth, Albrecht Geppert, Horst Gesing, Rigobert Schimmer
  • Method for producing diffused contacted and surface passivated semiconductor chips for semiconductor devices
    Patent number: 3965567
    Abstract: A method for producing diffused, contacted and surface passivated semiconductor chips for semiconductor devices, wherein after producing a semiconductor wafer with a given arrangement of layers and regions of different conductance and different conductivity types for a plurality of devices by doping with impurity forming elements, both of the major surfaces of the semiconductor wafer are provided with respective metal layers and output electrodes are applied to both of the metal layers for the plurality of devices with the output electrodes being of such a thickness and overlying such areas of the metal layers so that the thickness of the electrodes will still be sufficient for further processing after a subsequent separation of the wafer into the plurality of chips and the major surfaces of the chips after separation, are completely covered by the output electrodes.
    Type: Grant
    Filed: June 28, 1974
    Date of Patent: June 29, 1976
    Assignee: Licentia Patent-Verwaltungs-G.m.b.H.
    Inventors: Wolfgang Beerwerth, Albrecht Geppert, Horst Gesing, Rigobert Schimmer