Abstract: A circuit configuration for an amplifier stage includes an input terminal for receiving an input signal, an output terminal to be connected to a capacitive load, a supply voltage terminal for connection to a direct voltage and at least one reference potential terminal to be connected to the capacitive load. An amplifier quadrupole for amplifying the input signal has a first output lead, a first input lead connected to the input terminal, a second input lead connected to the at least one reference potential terminal, and a second output lead connected to the at least one reference potential terminal. At least one self-conducting FET for accelerated charging of the capacitive load has a gate lead connected to the first output terminal, a drain lead connected to the supply voltage terminal, and a source lead connected to the output terminal. At least one ohmic resistor is connected between the first output lead and the supply voltage terminal.