Horst Leuschner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: An N-bit programmable divider comprising N "T" flip-flops, N load gates, N-2 enable gates, an output JK flip-flop and a least-significant-bit input inverter; the least-significant-bit flip-flop being enabled by Q of said output flip-flop, the second-least-significant-bit flip-flop being enabled by Q of said least-significant-bit flip-flip, each of said remaining T flip-flops being enabled by NORed Q outputs of all less-significant-bit flip-flops, said output flip-flop having a J input only when the outputs of said N T flip-flops are indicative of a count of 2 and having a K input only with a Q output of said output flip-flop; the divider being loaded by application during Q of the output flip-flop of the complement of the least-significant-bit signal to the clear of the least-significant-bit T flip-flop and higher-significant-bit signals to preset of respective higher-significant-bit T flip-flops.
Abstract: A plural bit-stage synchronous counter/divider wherein each bit-stage comprises four multiple-input inverting gates in flip-flop configuration with the output of the first and second gates connected to one of the multiple inputs of the third and fourth gates respectively, one of the inputs of each of said first and second gates connected to a clock pulse line, the outputs of said third and fourth gates connected to a second input of said multiple inputs of each of said second and fourth gates and of said first and third gates respectively and third inputs of said multiple inputs of said third and fourth gates connected to clear and preset lines respectively and a clock pulse generator means providing clock pulses of a length between one and two times the propagation delay period of the slowest of said gates.
Abstract: The specification discloses various embodiments of solid state television channel-number display systems for use with television channel selection systems. The systems provide channel-number dislay with selection systems providing sequential and/or parallel access of television channels by operation of simple pushbutton or sense touch switches on the control panel of the television set, as well as sequential or parallel access of the channels through operation of remote control units. The selected television channel-number may be displayed in the parallel access mode by illuminating the actuated parallel access switch, or by the utilization of seven segment numerical displays with either the sequential or parallel access modes. The system enables selected television channels to be skipped during the sequential access mode. The system enables the operator to selectively choose which VHF and UHF channels may be selected by the system with display of the channel-number of the selected channel.