Abstract: A method for inserting an asynchronous 139,264 kbit/s signal into a 155,520 kbit/s signal interlaces an asynchronous 139,264 kbit/s signal from the European digital signal hierarchy into the frame structure of a 155,520 kbit/s signal STM-1 of a network node interface NNI. Bits that are compiled in the form of a virtual container VC-4 in a sub-frame are inserted into the frame structure, which sub-frame is composed of 9 sections each having respectively 261 sub-sections of 1 byte or, respectively, 8 bits each. The first sub-section is reserved for a path overhead (POH). The remaining 260 sub-sections are inventively subdivided into 20 blocks having a first part (W, X, Y, Z) of 1 byte for auxiliary signals and having a second part of 12 bytes composed of information bits (I). This method can be employed at a network node interface NNI in a synchronous digital hierarchy.

Abstract: Method for transmitting a digital broadband signal in a tributary unit concatenation via a network of a synchronous digital multiplex hierarchy. A pointer for positional identification in a frame is allocated to the first tributary unit in a tributary unit concatenation; instead of a pointer, the further tributary units receive a concatenation indicator. Every cross-connect equipment along a transmission link recognizes the tributary unit concatenation and forwards the tributary units thereof in the correct sequence. When a clock matching is required in the case of a first tributary unit, a pointer skip is initiated at all further tributary units. This requires hardware and software. This is eliminated when all tributary units (TU-12.sub.1 through TU-12.sub.5) containing the broadband signal (DSa) have a pointer (PTR1 through PTR5) having the value of the positional identification of the first tributary unit (TU-12.sub.1) allocated to them. The individual tributary units (TU-12.sub.1 through TU-12.sub.

Abstract: A two-layer cavity floor construction comprising a base layer of profile element panels with a plurality of passage-forming spacer elements and a surface layer which combine to provide a minimal overall height with particularly good noise and footstep insulation. The base layer is formed from a noise-insulating material preferably based on polyurethane bound in a polyurethane foam.

Abstract: In a synchronizing device for a TDM system which operates at a high speed, in order to be able to use a slower, energy-saving circuit technique, in the event of n possible phase positions, the TDM signal is split between n parallel shift registers. The outputs of the shift registers are connected to a frame code word recognition circuit. During a synchronization process, the slower-operating clock pulse train of the shift registers is delayed by the period of the received clock pulse train. As a result, the next possible phase position is checked. This procedure is repeated until the frame code word recognition circuit emits a synchronization signal.

Abstract: A multiplex unit for multiplexing plesiochronous digital signals has a monitoring device for signalling the loss of input signals on one or more channels being multiplexed. Upon recognition of a lost signal in one or more channels, an alarm indication signal is substituted for the information signals in that channel and a synthetic justification signal is produced which replaces the justification information in such channel. The synthetic justification information gives the alarm indication signal the correct pulse repetition rate in the outgoing channel of the multiplex unit.

Abstract: A time division demultiplexer for demultiplexing synchronous digital signals which are interleaved wordwise comprising a shift register of length (m + 1) .multidot. n, where n is the number of bits/word and m is the number of interleaved signals, having a control unit and a first and second store having a total capacity of m .multidot. n bits and each having m parallel inputs and m outputs; said shift register having an output tap every n bits, said first store having m .multidot. q storage elements and said second store having m .multidot. r storage elements, where q and r are integers and q + r = n; said first store being loaded by the first q bits of m words appearing at said shift register input point and on the succeeding m - 1 of said taps counting from said input point of said shift register; said second store being loaded with the second r bits of said m words appearing at said output point and the preceding m - 1 of said taps of said shift register; said second store being loaded approximately (m .