Abstract: An n-bit prefix tree adder includes n prefix trees, each associated with a bit position of the adder and including a number of computation stages. The computation stages for each of the bit positions include a sum computation stage implemented in logic circuitry. For a subset of the bit positions, the corresponding sum computation logic circuitry computes a sum based at least in part on group-generate, group-transmit and intermediate carry signals. Advantageously, the sum computation logic circuitry is configured to exploit differences in delay associated with generation of the group-generate, group-transmit and intermediate carry signals, so as to reduce the total computational delay of the adder.

Abstract: A first adder-subtracter combines the first input with the largest positive number capable of being represented by the number of bits in the datapath. A second adder-subtracter operating in parallel with the first adder-subtracter combines the first input with the largest negative number capable of being represented by the number of bits in the datapath. A third adder-subtracter combines the first, second, and third inputs and operates in parallel with the first and second adder-subtracters. A carry/sign detector circuit operating in parallel with all three adder-subtracters determines the sign and the carry of the sum of the second and third inputs.

Abstract: An unsigned integer comparator for use when comparing an n-bit received signal (such as an address) with an n-bit known signal ("comparison address"). The first stage of the comparator may be configured in advance, since the values of both a "comparison signal" and a "select signal" are known a priori. When the "current signal" arrives, the bits of this signal are then compared against the associated bits of the comparison signal. Subsequent stages of the comparator perform comparison operations of increasing length, dependent upon the outcome of the previous stage (i.e., a first set of 2-bit comparisons, then 4-bit, 8-bit, etc.), until the entire n-bit integers are ultimately compared and a final output is generated.

Abstract: A flag generating circuit that uses a feedback mechanism to set or reset a flag associated with two systems with asynchronous clocks is provided. Upon receipt of a set flag (or reset flag) signal, the circuit immediately isolates the signal after setting (or resetting) the flag to prevent race conditions between the systems. The clock associated with the setting system is synchronously started when waiting to set the flag and synchronously stopped when waiting for the flag to be reset. The clock associated with the resetting system is synchronously started when waiting to reset the flag and synchronously stopped when waiting for the flag to be set.

Abstract: An integrated circuit includes an n-bit counter having a plurality of k subcounters where both n and k are integers. At least one of the subcounters includes a switchable device adapted to receive a carry-out signal from an adjacent subcounter as a first input, a test carry signal as a second input, and a control input, the switchable device being capable of providing one of its inputs as an output, the control input capable of controlling selection of the output which is a carry signal. The subcounter also includes an n/k-bit counter, the n/k-bit counter receiving the carry signal and providing n/k output bits, and logic for combining the n/k-bits output from the n/k bit counter with the carry-out signal from an adjacent subcounter to provide an output that is a carry-out signal from the subcounter. The logic introducing a single gate delay between the carry-out signal from the adjacent subcounter and the carry-out signal from the subcounter.

Abstract: In accordance with the present invention, a method and apparatus are provided for controlling an N-bit barrel shifter to shift the bits of an input word by a shift value. The method includes the steps of performing a ones' complement of an m-bit binary representation of a shift value to generate an input when the shift direction takes on a first direction and passing the binary representation of the shift value as the input when the shift direction takes on a second direction. Decoding the input into 2.sup.m control signals and generating a plurality of groups of control signals from the 2.sup.m control signals. Selecting one of the plurality of groups of control signals as the control activation for the barrel shifter. The apparatus provides bits of a binary representation of the shift value are passed through a plurality of exclusive OR gates and provided as inputs to a first decoder. The first decoder decodes the inputs into a plurality of bits used as control signals.

Abstract: An N-bit binary synchronous counter includes K counter stages, with each stage including N/K flip-flops or other suitable storage elements. A given one of the counter stages receives a carry-in signal generated by another counter stage or by a carry logic circuit. The given counter stage includes a selection circuit for selecting one of two precomputed values for application to an input of a storage element in that stage based on a value of the carry-in signal. The selection circuit may include a two-input multiplexer for each of the N/K storage elements of the given counter stage. The jth multiplexer includes a first input coupled to an output of the jth storage element, and a second input coupled to an output of a logic circuit. The logic circuit generates a logic function based on the output of the jth storage element and other lower significant storage elements in the stage.

Abstract: A digital signal processor architecture particularly adapted for performing fast Fourier Transform algorithms efficiently. The architecture comprises dual, parallel multiply and accumulate units in which the output of the multiplier circuit portion of each MAC is cross-coupled to an input of the adder unit of the other MAC as well as to an input of the adder unit of the same MAC to which the multiplier belongs.

Abstract: A multiplier generates an array of partial products. The partial products are reduced in the more significant side of the array assuming a carry-out from the less significant side of the array as taking on a first state to produce a first set of reduced products. The partial products are also reduced in the more significant side of the array assuming a carry-out from the less significant side of the array as taking on a second state to produce a second set of reduced products. Both sets of reduced partial products are generated in parallel with the carry-out from the least significant side. The first set of reduced products are selected as the reduced products of the more significant side of the array when the carry-out from the less significant side of the array takes on the first state. The second set of reduced products are selected as the reduced products of the more significant side of the array when the carry-out from the less significant side of the array takes on the second state.