Abstract: In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in Vt after erasure. A memory array includes memory cells arranged in an array, a plurality of word lines, and a plurality of bit lines and main bit lines. The memory array also includes a usable region which can store data and an isolation region which cannot store data. Each bit line provided in the usable region is connected via a select transistor to the corresponding main bit line. At least one main bit line is connected not only to a bit line of the usable region, but also to a bit line of the isolation region via a select transistor.

Abstract: In a semiconductor memory device, a voltage rise due to IR-DROP is suppressed which occurs when a ground voltage is applied to a memory cell during a program operation. Discharge transistors are provided between the ground and bit lines connected to the source and drain of the memory cell. The discharge transistors receive mutually independent discharge control signals which are generated and outputted from a DS decoder driver at the respective gates thereof. To the bit line which applies the ground voltage to the memory cell, the ground voltage can be set using the discharge transistor.

Abstract: In a semiconductor memory device, a voltage rise due to IR-DROP is suppressed which occurs when a ground voltage is applied to a memory cell during a program operation. Discharge transistors are provided between the ground and bit lines connected to the source and drain of the memory cell. The discharge transistors receive mutually independent discharge control signals which are generated and outputted from a DS decoder driver at the respective gates thereof. To the bit line which applies the ground voltage to the memory cell, the ground voltage can be set using the discharge transistor.

Abstract: A drain voltage generator circuit includes a first switching element coupled between a first power supply voltage and an output end of the drain voltage generator circuit, a second switching element coupled in parallel to the first switching element and having a smaller current capability than that of the first switching element, and a control circuit for turning ON the second switching element and then the first switching element, and generates a voltage to supply to a drain of a memory cell. A source of the memory cell is set to be floated or grounded by a transistor.

Abstract: In a non-volatile semiconductor memory device, variations in voltage applied to a bit line when an erase voltage applying step is repeatedly executed are suppressed, thereby reducing variations in Vt after erasure. A memory array includes memory cells arranged in an array, a plurality of word lines, and a plurality of bit lines and main bit lines. The memory array also includes a usable region which can store data and an isolation region which cannot store data. Each bit line provided in the usable region is connected via a select transistor to the corresponding main bit line. At least one main bit line is connected not only to a bit line of the usable region, but also to a bit line of the isolation region via a select transistor.

Abstract: A memory cell transistor array is composed of a plurality of memory cells having three or more threshold voltage distribution states in a single electric charge accumulation portion. A program sequence control circuit associates each piece of data included in a data set composed of a plurality of data values with any threshold voltage distribution of the three or more threshold voltage distributions, to store the data in the memory cell, and when rewriting the data stored in the memory cell, shifting threshold voltage distributions used for data storage in one direction to perform the data rewrite operation.

Abstract: To implement a high reliability and large number of rewrite operations by optimizing reliability margins of both data “0” and data “1” or a reliability margin of one of the data “0” or data “1” with a circuit for monitoring a rewrite status and a circuit for changing a read condition corresponding to the number of rewrite operations based on a result of monitoring the rewritable status.