Patents by Inventor Hossain Pezeshki-Esfahani

Hossain Pezeshki-Esfahani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6711176
    Abstract: The method for converting cell-based ATM traffic to frame-based ATM traffic comprises assembling a group of one or more cells of a input cell stream which corresponds to an AAL5 PDU; extracting a user data payload of the AAL5 PDU, exclusive of any padding; constructing a frame-based ATM adaptation layer protocol data unit (FB-AAL PDU) having no padding using the AAL5 PDU payload; and segmenting the FB-AAL PDU into one or more frames to generate an output frame stream. The method provides an increase in bandwidth efficiency since the padding overhead required by AAL5 PDUs is eliminated when transferring data to, over or across a frame-based ATM network.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: March 23, 2004
    Assignee: Alcatel Canada Inc.
    Inventor: Hossain Pezeshki-Esfahani
  • Patent number: 6687254
    Abstract: The method and system for buffering packets such as ATM cells at a queueing point of a device which employs a connection-orientated communications protocol includes the steps of logically partitioning a memory into plural reserved buffer spaces allocated to traffic classes and a shared buffer space available to any connection; determining whether to store or discard a given packet based on predetermined discard criteria; and filling the reserved buffer space to a predetermined state of congestion before storing the given packet in the shared buffer space. Reserved buffer space congestion states are defined with respect to individual connections, groups of connections, and the total capacity of the reserved buffer space itself. Packets are discarded when any, or alternatively a specific combination, of corresponding congestion states occur, and the shared space is congested as well.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: February 3, 2004
    Assignee: Alcatel Canada Inc.
    Inventors: Esmond Ho, Tom Davis, Ganti Sudhakar, Kostic Predrag, Hossain Pezeshki-Esfahani, Charlie Sabry, Natalie Giroux
  • Patent number: 6647477
    Abstract: A data traffic management system that has the capability of writing data to the buffer memory at twice its normal rate. The data traffic management system uses a pointer structure that can reference either a single or a dual segment memory bank. A dual segment memory bank enhances the write capability of the data traffic management system by allowing two segments to be simultaneously written to both segment memory banks, with one segment being written to each bank. A pointer data structure with a single/dual indicator (S/D indicator) is used for referencing the memory banks. If the S/D indicator has a D entry, then a dual segment memory bank is addressed. The S/D indicator will have an S entry if a single segment memory bank is addressed. Based on the contents of the S/D indicator, either a single fixed size data segment is written to a single memory bank or two fixed size data segments are written to a dual segment memory bank.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: November 11, 2003
    Assignee: PMC-Sierra Ltd.
    Inventors: Mark W. Janoska, Henry Chow, Hossain Pezeshki-Esfahani
  • Publication number: 20030072260
    Abstract: A congestion management system that controls access to any shared resource by incoming data transmission units. The access can be controlled based on the particular connection associated with a data transmission unit. Every shared resource, such as a pool of buffer memory, is represented by a partition. The congestion management system is comprised of a plurality of connection data structures and a plurality of partition data structures. Each connection data structure represents a particular connection and, similarly, each partition data structure represents a particular partition. Each incoming DTU is associated with a single connection but may be allowed access to more than one partition. Each partition is associated with a shared resource and access to each partition is governed by the state of a partition data structure. If a partition data structure indicates that a specific threshold has been met, then access to the shared resource by other DTUs is denied.
    Type: Application
    Filed: October 4, 2001
    Publication date: April 17, 2003
    Inventors: Mark William Janoska, Henry Chow, Hossain Pezeshki-Esfahani
  • Patent number: 6539024
    Abstract: A method and apparatus is for buffering data cells in a queuing element is presented. Each queuing element includes a partitioned buffer, where the partitioned buffer includes a plurality of partitions. Each of the partitions stores data cells received by the queuing element. Storage of the data cells into the partitions is accomplished by using an array of logical queues. Each logical queue of the array of logical queues maps data cells corresponding to that logical queue to a particular partition of the plurality of partitions. More than one logical queue may map data cells to a particular partition. Each partition may include a reserved portion, where each logical queue that maps to the partition may map a portion of its data cells to the reserved portion. The resources of the reserved portion to which a logical queue maps data cells are reserved to that specific logical queue and cannot be utilized by other logical queues.
    Type: Grant
    Filed: March 26, 1999
    Date of Patent: March 25, 2003
    Assignee: Alcatel Canada Inc.
    Inventors: Mark William Janoska, Albert D. Heller, Hossain Pezeshki-Esfahani
  • Publication number: 20020066000
    Abstract: A data traffic management system that has the capability of writing data to the buffer memory at twice its normal rate. The data traffic management system uses a pointer structure that can reference either a single or a dual segment memory bank. A dual segment memory bank enhances the write capability of the data traffic management system by allowing two segments to be simultaneously written to both segment memory banks, with one segment being written to each bank. A pointer data structure with a single/dual indicator (S/D indicator) is used for referencing the memory banks. If the S/D indicator has a D entry, then a dual segment memory bank is addressed. The S/D indicator will have an S entry if a single segment memory bank is addressed. Based on the contents of the S/D indicator, either a single fixed size data segment is written to a single memory bank or two fixed size data segments are written to a dual segment memory bank.
    Type: Application
    Filed: October 4, 2001
    Publication date: May 30, 2002
    Inventors: Mark W. Janoska, Henry Chow, Hossain Pezeshki-Esfahani
  • Patent number: 6353618
    Abstract: A scheduling device for use in a packet-switched network, belonging to the class of non-work conserving or idling weighted round robin (WRR) arbiters, assigns a packet stream slots in a fixed-length time division multiple access (TDMA) frame by selecting free slots which are closest to ideal slot positions that would, if assigned, eliminate jitter or cell delay variation. The scheduler is able to simultaneously determine if a new constant bit rate connection requiring a predetermined bandwidth conforms to a leaky bucket or GCRA algorithm characterized by a peak packet or cell emission interval T=1/PCR and a packet or cell delay variation time, CDVT, i.e., whether the new connection is GCRA (T, CDVT) conformant.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: March 5, 2002
    Assignee: Alcatel Canada Inc.
    Inventors: Anthony Hung, Hossain Pezeshki-Esfahani, Tom Davis