Abstract: The invention concerns a 3D circuit design method implemented by a processing device involving partitioning a 2D circuit representation into two or more tiers, the 2D circuit representation defining circuit elements interconnected by interconnecting wire each weighted based on at least one of: its length; its propagation delay; and its priority level, the 2D circuit representation initially forming a first tier, the partitioning involving: a) selecting a first highest ranking wire, interconnecting at least first and second circuit elements in the first tier; b) moving one of the first and second circuit elements connected by the selected wire to a further tier of the 3D circuit representation and replacing the interconnecting wire with a connecting via between the first and further tiers; and c) repeating a) and b) for one or more further interconnecting wires of the first tier.

Abstract: The invention concerns a 3D circuit design method implemented by a processing device involving partitioning a 2D circuit representation into two or more tiers, the 2D circuit representation defining circuit elements interconnected by interconnecting wire each weighted based on at least one of: its length; its propagation delay; and its priority level, the 2D circuit representation initially forming a first tier, the partitioning involving: a) selecting a first highest ranking wire, interconnecting at least first and second circuit elements in the first tier; b) moving one of the first and second circuit elements connected by the selected wire to a further tier of the 3D circuit representation and replacing the interconnecting wire with a connecting via between the first and further tiers; and c) repeating a) and b) for one or more further interconnecting wires of the first tier.