Patents by Inventor Hossein Paravi

Hossein Paravi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8278702
    Abstract: A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: October 2, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: James Pan, Scott L. Hunt, Dean E. Probst, Hossein Paravi
  • Patent number: 8003522
    Abstract: A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion of the semiconductor region is removed through the exposed surface area of the semiconductor region. The thinner portions of the hard mask layer are removed to expose surface areas of the semiconductor region underlying the thinner portions. An additional portion of the semiconductor region is removed through all exposed surface areas of the semiconductor region thereby forming a trench having an upper portion that is wider than its lower portion.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: August 23, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Hui Chen, Ihsiu Ho, Stacy W. Hall, Briant Harward, Hossein Paravi
  • Publication number: 20100065904
    Abstract: A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.
    Type: Application
    Filed: September 16, 2008
    Publication date: March 18, 2010
    Inventors: James Pan, Scott L. Hunt, Dean E. Probst, Hossein Paravi
  • Publication number: 20100003823
    Abstract: A method for forming a semiconductor structure includes the following steps. A hard mask layer is formed over a semiconductor region. The hard mask layer has inner portions that are thinner than its outer portions, and the inner portions define an exposed surface area of the semiconductor region. A portion of the semiconductor region is removed through the exposed surface area of the semiconductor region. The thinner portions of the hard mask layer are removed to expose surface areas of the semiconductor region underlying the thinner portions. An additional portion of the semiconductor region is removed through all exposed surface areas of the semiconductor region thereby forming a trench having an upper portion that is wider than its lower portion.
    Type: Application
    Filed: December 3, 2008
    Publication date: January 7, 2010
    Inventors: Hui Chen, Ihsiu Ho, Stacy W. Hall, Briant Harward, Hossein Paravi
  • Publication number: 20090050958
    Abstract: A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient of phosphorous in silicon. An epitaxial layer is also disposed over the substrate. A device layer is disposed over the substrate, and over the spacer layer.
    Type: Application
    Filed: September 8, 2008
    Publication date: February 26, 2009
    Inventors: Qi Wang, Amber Crellin-Ngo, Hossein Paravi
  • Publication number: 20070059906
    Abstract: A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient of phosphorous in silicon. An epitaxial layer is also disposed over the substrate. A device layer is disposed over the substrate, and over the epitaxial and spacer layers.
    Type: Application
    Filed: November 3, 2006
    Publication date: March 15, 2007
    Inventors: Qi Wang, Amber Crellin-Ngo, Hossein Paravi
  • Patent number: 7132715
    Abstract: A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient of phosphorous in silicon. An epitaxial layer is also disposed over the substrate. A device layer is disposed over the substrate, and over the epitaxial and spacer layers.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: November 7, 2006
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Qi Wang, Amber Crellin-Ngo, Hossein Paravi
  • Publication number: 20050258481
    Abstract: A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient of phosphorous in silicon. An epitaxial layer is also disposed over the substrate. A device layer is disposed over the substrate, and over the epitaxial and spacer layers.
    Type: Application
    Filed: May 21, 2004
    Publication date: November 24, 2005
    Inventors: Qi Wang, Amber Crellin-Ngo, Hossein Paravi