Patents by Inventor Hou-Chang Kuo

Hou-Chang Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8497571
    Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a top surface, a bottom surface and a plurality of apertures formed at the bottom surface, wherein the bottom surface of the insulating layer comprises a disposing area and a non-disposing area. Each of the apertures is located at the disposing area and comprises a lateral wall and a base surface. A first thickness is formed between the base surface and the insulating layer, a second thickness is formed between the top surface and the bottom surface, and the second thickness is larger than the first thickness. The chip disposed on the top surface comprises a chip surface and a plurality of bumps. The heat dissipation paste at least fills the apertures and contacts the base surface.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: July 30, 2013
    Assignee: Chipbond Technology Corporation
    Inventors: Chin-Tang Hsieh, Hou-Chang Kuo, Dueng-Shiu Tzou, Chia-Jung Tu, Gwo-Shyan Sheu
  • Patent number: 8471372
    Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, wherein the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a first insulating portion and a second insulating portion, the first insulating portion comprises a first upward surface, a first downward surface, a first thickness and a recess formed on the first downward surface, wherein the recess comprises a bottom surface. The second insulating portion comprises a second upward surface, a second downward surface and a second thickness larger than the first thickness. The trace layer is at least formed on the second insulating portion, the chip disposed on top of the substrate is electrically connected with the trace layer and comprises a plurality of bumps, and the heat dissipation paste is disposed at the recess.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: June 25, 2013
    Assignee: Chipbound Technology Corporation
    Inventors: Chin-Tang Hsieh, Hou-Chang Kuo, Dueng-Shiu Tzou, Chia-Jung Tu, Gwo-Shyan Sheu
  • Publication number: 20120074545
    Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, wherein the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a first insulating portion and a second insulating portion, the first insulating portion comprises a first upward surface, a first downward surface, a first thickness and a recess formed on the first downward surface, wherein the recess comprises a bottom surface. The second insulating portion comprises a second upward surface, a second downward surface and a second thickness larger than the first thickness. The trace layer is at least formed on the second insulating portion, the chip disposed on top of the substrate is electrically connected with the trace layer and comprises a plurality of bumps, and the heat dissipation paste is disposed at the recess.
    Type: Application
    Filed: June 20, 2011
    Publication date: March 29, 2012
    Inventors: Chin-Tang Hsieh, Hou-Chang Kuo, Dueng-Shiu Tzou, Chia-Jung Tu, Gwo-Shyan Sheu
  • Publication number: 20020195721
    Abstract: In a cavity down BGA packaging structure, a circuit substrate is bonded onto a heat spreader. A cavity formed is formed in the circuit substrate into which a chip is bonded onto the heat spreader. The circuit substrate has at least an insulating layer, a patterned wiring layer, and a via electrically connected to the heat spreader. A first ground pad, ball pad, and first contact pad are defined on the patterned wiring layer, wherein the first ground pad is spaced apart from and electrically connected to the via. The chip comprises at least a second contact pad and a second ground pad respectively connected to the first contact pad and the heat spreader. An encapsulant material encapsulates the cavity, the chip, and the first and second contact pads. A plurality of solder balls are attached to the first ground pad and ball pad.
    Type: Application
    Filed: March 5, 2002
    Publication date: December 26, 2002
    Inventors: Chun-Chi Lee, Jaw-Shiun Hsieh, Yao-Hsin Feng, Hou-Chang Kuo, Kuan-Neng Liao, Yu-Hsien Lin
  • Patent number: 6483187
    Abstract: A heat-spread substrate consisting of a metal heat spreader and a substrate is disclosed. The metal heat spreader has a surface with a cavity, which is adapted for supporting a die. Such surface further includes a ground ring arranged at the periphery of the cavity; a substrate-supporting surface surrounding the periphery of the ground ring; a plurality of first ground pads arranged at the periphery of the substrate-supporting surface; and a plurality of second ground pads arranged on the substrate-supporting surface and protruding it. The substrate is provided on the substrate-supporting surface having a plurality of through holes. The through holes corresponds to the first ground pad so as to make it be located therein, respectively. The substrate further includes a plurality of mounting pads and a plurality of ball pads, in which the mounting pads are close to the cavity, and the first ground pad, the second ground pads and the ball pads are formed in the form of ball grid array and are coplanar roughly.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: November 19, 2002
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Shin-Hua Chao, Kuan-Neng Liao, Yao-Hsin Feng, Hou-Chang Kuo