Abstract: This disclosure provides a scheduling apparatus and method, and a related device. The scheduling apparatus includes a dispatcher coupled to an execution apparatus. The dispatcher includes a plurality of first buffers, each of the plurality of first buffers is configured to cache target tasks of one task type, the target tasks include a thread subtask and a cache management operation task, and the cache management operation task indicates to perform a cache management operation on input data or output data of the thread subtask. The dispatcher is configured to: receive a plurality of first target tasks, and cache the plurality of first target tasks in the plurality of first buffers based on task types; and dispatch a plurality of second target tasks to the execution apparatus.

Abstract: A multi-core processor and a related inter-core communication method are provided. The multi-core processor includes an inter-core communication module and a plurality of processor cores. The plurality of processor cores include N first processor cores. Each of the N first processor cores is configured to: execute a first task to generate operation information, where the operation information includes a completion identifier of the first task, and one or more of a processor core identifier of the first processor core, an inter-core synchronization mode, or association information of the first task; and send the operation information to the inter-core communication module. The inter-core communication module is configured to: determine M second processor cores from the plurality of processor cores based on N pieces of operation information, and separately send the completion identifier to the M second processor cores. Inter-core communication can be performed more efficiently and cost-effectively.

Abstract: In a synchronization method, a first processor creates a first synchronization object for a first synchronization event. The first synchronization object includes an identifier of a first synchronization register. A value of the first synchronization register includes a first value or a second value. The first value is used to indicate that the first synchronization event does not occur, and the second value is used to indicate that the first synchronization event occurs. The first processor includes a first CPU. The second processor determines, based on the value of the first synchronization register, whether the first synchronization event occurs. The second processor includes a first NPU.

Abstract: In a synchronization method, a first processor creates a first synchronization object for a first synchronization event. The first synchronization object includes an identifier of a first synchronization register. A value of the first synchronization register includes a first value or a second value. The first value is used to indicate that the first synchronization event does not occur, and the second value is used to indicate that the first synchronization event occurs. The first processor includes a first CPU. The second processor determines, based on the value of the first synchronization register, whether the first synchronization event occurs. The second processor includes a first NPU.

Abstract: A task processing method, a processing apparatus, and a computer system are provided. Implementation of the method includes: generating, by a first processing apparatus, a plurality of tasks, and determining task description information of the plurality of tasks, where the task description information of the plurality of tasks is used to indicate a dependency relationship between the plurality of tasks; sending an instruction to a second processing apparatus, where the instruction includes the plurality of tasks and the task description information of the plurality of tasks; and receiving the instruction, and processing the plurality of tasks based on the dependency relationship between the plurality of tasks. The method can effectively reduce a waiting delay, fully exploit a computing capability of an acceleration chip, and improve task processing efficiency.

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

Abstract: In a synchronization method, a first processor creates a first synchronization object for a first synchronization event. The first synchronization object includes an identifier of a first synchronization register. A value of the first synchronization register includes a first value or a second value. The first value is used to indicate that the first synchronization event does not occur, and the second value is used to indicate that the first synchronization event occurs. The first processor includes a first CPU. The second processor determines, based on the value of the first synchronization register, whether the first synchronization event occurs. The second processor includes a first NPU.

Abstract: A data processing method and apparatus are disclosed. In various embodiments, R groups of proposal region sequences are obtained. Each group of proposal region sequence includes a plurality of proposal regions. In those embodiments, a VRPAC instruction is invoked to calculate an area of each proposal region in each group of proposal region sequence. For a jth group of proposal region sequence in the R groups of proposal region sequences, a VIOU instruction and a VAADD instruction are invoked to determine j suppression matrices of the jth group of proposal region sequence and determine a suppression vector of the jth group of proposal region sequence based on the j suppression matrices. In those embodiments, an unsuppressed proposal region is determined based on a suppression vector of each group of proposal region sequence.

Abstract: A data processing method implemented by a computer device, includes generating a target task including a buffer application task or a buffer release task, when the target task is the buffer application task, a first buffer corresponding to the buffer application task is used when the second task is executed, or when the target task is the buffer release task, a second buffer corresponding to the buffer release task is used when the first task is executed, obtaining a buffer entry corresponding to the target task after a preceding task of the target task is executed and before a successive task of the target task is executed, where the buffer entry includes a memory size of a buffer corresponding to the target task, a memory location of the buffer, and a memory address of the buffer, and executing the target task to apply for or release the buffer.

Abstract: A data processing method implemented by a computer device, includes generating a target task including a buffer application task or a buffer release task, when the target task is the buffer application task, a first buffer corresponding to the buffer application task is used when the second task is executed, or when the target task is the buffer release task, a second buffer corresponding to the buffer release task is used when the first task is executed, obtaining a buffer entry corresponding to the target task after a preceding task of the target task is executed and before a successive task of the target task is executed, where the buffer entry includes a memory size of a buffer corresponding to the target task, a memory location of the buffer, and a memory address of the buffer, and executing the target task to apply for or release the buffer.

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

Abstract: Embodiments of the present invention disclose a matrix multiplier, and relate to the field of data computing technologies, so as to divide two matrices into blocks for computation. The matrix multiplier includes: a first memory, a second memory, an operation circuit, and a controller, where the operation circuit, the first memory, and the second memory may perform data communication by using a bus; and the controller is configured to control, according to a preset program or instruction, a first matrix and a second matrix to be divided into blocks, and control the operation circuit to perform a multiplication operation on corresponding blocks in the first memory and the second memory based on block division results of the controller. The matrix multiplier may be configured to perform a multiplication operation on two matrices.

Abstract: A data processing method implemented by a computer device, includes generating a target task including a buffer application task or a buffer release task, when the target task is the buffer application task, a first buffer corresponding to the buffer application task is used when the second task is executed, or when the target task is the buffer release task, a second buffer corresponding to the buffer release task is used when the first task is executed, obtaining a buffer entry corresponding to the target task after a preceding task of the target task is executed and before a successive task of the target task is executed, where the buffer entry includes a memory size of a buffer corresponding to the target task, a memory location of the buffer, and a memory address of the buffer, and executing the target task to apply for or release the buffer.

Abstract: A task processing method, a processing apparatus, and a computer system are provided. Implementation of the method includes: generating, by a first processing apparatus, a plurality of tasks, and determining task description information of the plurality of tasks, where the task description information of the plurality of tasks is used to indicate a dependency relationship between the plurality of tasks; sending an instruction to a second processing apparatus, where the instruction includes the plurality of tasks and the task description information of the plurality of tasks; and receiving the instruction, and processing the plurality of tasks based on the dependency relationship between the plurality of tasks. The method can effectively reduce a waiting delay, fully exploit a computing capability of an acceleration chip, and improve task processing efficiency.

Abstract: A data processing method and apparatus are disclosed. The method includes: obtaining R groups of proposal region sequences, where each group of proposal region sequence includes a plurality of proposal regions; invoking a VRPAC instruction to calculate an area of each proposal region in each group of proposal region sequence; for a jth group of proposal region sequence in the R groups of proposal region sequences, invoking a VIOU instruction and a VAADD instruction to determine j suppression matrices of the jth group of proposal region sequence and determine a suppression vector of the jth group of proposal region sequence based on the j suppression matrices; and determining an unsuppressed proposal region based on a suppression vector of each group of proposal region sequence. The method reduces invoked instructions, reduces instruction execution steps, and shortens a time used in NMS calculation.