Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.

Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.

Abstract: An electrostatic discharge protection structure includes a semiconductor substrate and a first n-type well region, a p-type well region, a first p-type doped region, a second p-type doped region, and an isolation structure disposed in the semiconductor substrate. The p-type well region is located adjacent to the first n-type well region. The first p-type doped region and the second p-type doped region are located above the first n-type well region and the p-type well region, respectively. A first portion of the isolation structure is located between the first p-type doped region and the second p-type doped region in a horizontal direction. An edge of the first n-type well region is located under the first portion. A distance between the first p-type doped region and the edge of the first n-type well region in the horizontal direction is less than a length of the first portion in the horizontal direction.

Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a gate structure, a source doped region, a drain doped region, source silicide patterns, and drain silicide patterns. The gate structure is disposed on the semiconductor substrate. The source doped region and the drain doped region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction, respectively. The source silicide patterns are disposed on the source doped region. The source silicide patterns are arranged in a second direction and separated from one another. The drain silicide patterns are disposed on the drain doped region. The drain silicide patterns are arranged in the second direction and separated from one another. The source silicide patterns and the drain silicide patterns are arranged misaligned with one another in the first direction.

Abstract: A semiconductor structure for electrostatic discharge (ESD) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. The first doped well is disposed in the substrate and has a first conductive type. The source doped region is disposed in the substrate and has a second conductive type opposite to the first conductive type. The drain doped region is disposed in the substrate and has the second conductive type. The gate structure is disposed on the substrate and between the source doped region and the drain doped region. The gate structure is separated from the source doped region.

Abstract: A grounded gate NMOS transistor includes a P-type substrate, P-well region in the P-type substrate, and a gate finger traversing the P-well region. The gate finger has a first spacer on a first sidewall and a second spacer on a second sidewall opposite to the first sidewall. An N+ drain doping region is disposed in the P-type substrate and is adjacent to the first sidewall of the gate finger. The N+ drain doping region is contiguous with a bottom edge of the first spacer. An N+ source doping region is disposed in the P-type substrate opposite to the N+ drain doping region. The N+ source doping region is kept a predetermined distance from a bottom edge of the second spacer. A P+ pick-up ring is disposed in the P-well region and surrounds the gate finger, the N+ drain doping region, and the N+ source doping region.

Abstract: An ESD protection device on a substrate includes a base doped region of a first conductivity type. A first inter doped region of a second conductivity type is in the base doped region. A drain region of the second conductivity type in the first inter doped region is connected to a first electrode terminal. An inserted doped region of the first conductivity type is in the drain region. A second inter doped region of the second conductivity type is in the base doped region. A source region of the second conductivity type is in the second inter doped region. A substrate-surface doped region of the first conductivity type in the substrate is adjacent to or in contact with the source region. A gate structure is between the drain and source regions in the substrate. The substrate-surface doped region and the source region are connected to a second electrode terminal.

Abstract: A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. The shallow trench isolation is disposed in the substrate and surrounds the fin shaped structure. The diffusion break structure is disposed in the fin shaped structure, and the gate electrode is disposed across the fin shaped structure.

Abstract: An electrostatic discharge (ESD) device includes a gate structure, disposed on a substrate. A drain doped region of a first conductive type is in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration. A first doped region of the first conductive type is disposed within the drain doped region and being at least distant from the gate structure by a distance. The first doped region has a second impurity concentration lower than the first impurity concentration.

Abstract: A semiconductor device comprises a fin shaped structure, a shallow trench isolation, a diffusion break structure and a gate electrode. The fin shaped structure is disposed on a substrate. The shallow trench isolation is disposed in the substrate and surrounds the fin shaped structure. The diffusion break structure is disposed in the fin shaped structure, and the gate electrode is disposed across the fin shaped structure.

Abstract: An electrostatic discharge (ESD) device includes a gate structure, disposed on a substrate. A drain doped region of a first conductive type is in the substrate, adjacent to a first side of the gate structure, wherein the drain doped region has a first impurity concentration. A first doped region of the first conductive type is disposed within the drain doped region and being at least distant from the gate structure by a distance. The first doped region has a second impurity concentration lower than the first impurity concentration.

Abstract: An ESD protection device on a substrate includes a base doped region of a first conductivity type. A first inter doped region of a second conductivity type is in the base doped region. A drain region of the second conductivity type in the first inter doped region is connected to a first electrode terminal. An inserted doped region of the first conductivity type is in the drain region. A second inter doped region of the second conductivity type is in the base doped region. A source region of the second conductivity type is in the second inter doped region. A substrate-surface doped region of the first conductivity type in the substrate is adjacent to or in contact with the source region. A gate structure is between the drain and source regions in the substrate. The substrate-surface doped region and the source region are connected to a second electrode terminal.

Abstract: A semiconductor structure for electrostatic discharge (ESD) protection is provided. The semiconductor structure includes a substrate, a first doped well, a source doped region, a drain doped region, and a gate structure. The first doped well is disposed in the substrate and has a first conductive type. The source doped region is disposed in the substrate and has a second conductive type opposite to the first conductive type. The drain doped region is disposed in the substrate and has the second conductive type. The gate structure is disposed on the substrate and between the source doped region and the drain doped region. The gate structure is separated from the source doped region.