Abstract: A method for manufacturing the AlGaInP LED having a vertical structure is provided, including: growing, epitaxially, a buffer layer, an n-type contact layer, an n-type textured layer, a confined layer, an active layer, a p-type confined layer and a p-type window layer in that order on a temporary substrate, to form a texturable epitaxial layer; forming a transparent conducting film with periodicity on the p-type window layer of the epitaxial layer, forming a regulated through-hole on the transparent conducting film, and filling the through-hole with a conducting material; forming a total-reflection metal layer on the transparent conducting film; bonding a permanent substrate with the texturable epitaxial layer via a bonding layer, and bring the total-reflection metal layer into contact with the bonding layer; removing the temporary substrate and the buffer layer; forming an n-type extension electrode on the exposed n-type contact layer; removing the n-type contact layer, and forming a pad on the n-type textur

Abstract: A method for packaging micromachined devices fabricated by MEMS and semiconductor process is disclosed in this invention. The method employed etching technique to etch a trench surrounding the micromachined components on each chip of the first wafer down to the bottom interconnection metal layer. The said trench can accommodate the solder of flip-chip packaging. On each chip of the second wafer, or called as the second chip, a surrounding copper pillar wall corresponding to the trench on the first chip is deposited. By wafer-level packaging, the trench on the first chip is aligned to the pillar wall, and then bonded together with elevated temperature. The face-to-face chamber formed between two chips can allow the movement of the micromachined structures. Further, the signal or power connections between two chips can be established by providing several discrete pillar bumps.

Abstract: A method for manufacturing the AlGaInP LED having a vertical structure is provided, including: growing, epitaxially, a buffer layer, an n-type contact layer, an n-type textured layer, a confined layer, an active layer, a p-type confined layer and a p-type window layer in that order on a temporary substrate, to form a texturable epitaxial layer; forming a transparent conducting film with periodicity on the p-type window layer of the epitaxial layer, forming a regulated through-hole on the transparent conducting film, and filling the through-hole with a conducting material; forming a total-reflection metal layer on the transparent conducting film; bonding a permanent substrate with the texturable epitaxial layer via a bonding layer, and bring the total-reflection metal layer into contact with the bonding layer; removing the temporary substrate and the buffer layer; forming an n-type extension electrode on the exposed n-type contact layer; removing the n-type contact layer, and forming a pad on the n-type textur

Abstract: A structure and method of forming pillar bumps with controllable shape and size are provided, which use polishing planarization technology to eliminate shape difference among pillar bumps on a wafer and die, thus yield the pillar bumps with design shape and size.

Abstract: This invention disclosed a method to strengthen structure and enhance sensitivity for CMOS-MEMS micro-machined devices which include micro-motion sensor, micro-actuator and RF switch. The steps of the said method contain defining deposited region by metal and passivation layer, forming a cavity for depositing metal structure by lithography process, depositing metal structure on the top metal layer of micromachined structure by Electroless plating, polishing process and etching process. The method aims at strengthening structures and minimizing CMOS-MEMS device size. Furthermore, this method can also be applied to inertia sensors such as accelerometer or gyroscope, which can enhance sensitivity and capacitive value, and deal with curl issues for suspended CMOS-MEMS devices.

Abstract: A method for packaging micromachined devices fabricated by MEMS and semiconductor process is disclosed in this invention. The method employed etching technique to etch a trench surrounding the micromachined components on each chip of the first wafer down to the bottom interconnection metal layer. The said trench can accommodate the solder of flip-chip packaging. On each chip of the second wafer, or called as the second chip, a surrounding copper pillar wall corresponding to the trench on the first chip is deposited. By wafer-level packaging, the trench on the first chip is aligned to the pillar wall, and then bonded together with elevated temperature. The face-to-face chamber formed between two chips can allow the movement of the micromachined structures. Further, the signal or power connections between two chips can be established by providing several discrete pillar bumps.

Abstract: A gate bracket is formed of a planar web in which two rectangular portions along two edges of the web are bent to define a first pair of perpendicular flanges, and two other rectangular portions are bent from an inner portion of the web to form a second pair of perpendicular flanges. The flanges of the first pair are spaced from the flanges of the second pair by a distance corresponding to the dimensions of the structural members used to construct the gate. The invention provides a rigid bracket of simpler and lighter construction than prior art brackets.

Abstract: A MEMS-based fabrication process is disclosed to fabricate a hollow seamless drug-eluting stent. This stent fabrication process is characterized by using a photolithography process, a composite electroplating process, and a polishing process to mass-produce drug-eluting seamless stents. Combining a multi-layers photolithography process with a multi-layers composite electroforming process could make the formation of micro-holes, micro-caves, or micro-trenches integrated with this hollow seamless eluting-stent for any anti-thrombosis drug loading or filling.

Abstract: A method of forming a selective area semiconductor compound epitaxy layer is provided. The method includes the step of using two silicon-containing precursors as gas source for implementing a process of manufacturing the selective area semiconductor compound epitaxy layer, so as to form a semiconductor compound epitaxy layer on an exposed monocrystalline silicon region of a substrate.

Abstract: This invention is characteristic of combining an electroplating process with a polishing process to uniformly fabricate multi-layer flip chip copper pillar. All kinds of flip chip copper pillar with varied shapes and sizes are able to be defined by using multi-layer photolithography process commonly utilized in the semiconductor processes. After that, use both exposure and alignment procedures to accurately define multi-layer photoresist's patterns on the substrate. Some designated metallic materials are then electroplated on those completed well-defined patterns during the last photolithography process by means of an electroplating process. A polishing process follows the electroplating to level the rugged solder bumps, resulted from the impact on the certain changeable and inevitable electroplating parameters.