Abstract: A light emitting diode structure includes a metal reflective layer, a first transparent electrically-conductive layer, a dielectric layer, second transparent electrically-conductive layers, a first type semiconductor layer, an active layer and a second type semiconductor layer. The metal reflective layer has first concave sections. The first transparent electrically-conductive layer is conformally formed over the first concave sections of the metal reflective layer. The dielectric layer is formed over the first transparent electrically-conductive layer and has through holes to expose the first transparent electrically-conductive layer. The second transparent electrically-conductive layers are formed over the dielectric layer, and connected with the first transparent electrically-conductive layer via the through holes. Each second transparent electrically-conductive layer is connected to the first transparent electrically-conductive layer to form a T-shaped cross section in each first concave section.

Abstract: A light-emitting diode includes: a semiconductor epitaxial structure including a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, an active layer between the first and second semiconductor layers; a first electrode electrically coupled to the first semiconductor layer and including a plurality of first sub-electrodes, wherein the plurality of first sub-electrodes are divided into one or more groups, and any two adjacent first sub-electrodes in the same group have a same projection distance; a second electrode disposed over and electrically coupled to the second semiconductor layer; a third electrode coupled to the plurality of first sub-electrodes and including one or more third sub-electrodes, wherein one of the third sub-electrodes corresponds to one of said one or more groups of the first sub-electrodes and connects first sub-electrodes in the group; and a fourth electrode coupled to the second electrode.

Abstract: A light-emitting diode includes: a semiconductor epitaxial structure including a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, an active layer between the first and second semiconductor layers; a first electrode electrically coupled to the first semiconductor layer and including a plurality of first sub-electrodes, wherein the plurality of first sub-electrodes are divided into one or more groups, and any two adjacent first sub-electrodes in the same group have a same projection distance; a second electrode disposed over and electrically coupled to the second semiconductor layer; a third electrode coupled to the plurality of first sub-electrodes and including one or more third sub-electrodes, wherein one of the third sub-electrodes corresponds to one of said one or more groups of the first sub-electrodes and connects first sub-electrodes in the group; and a fourth electrode coupled to the second electrode.

Abstract: A light-emitting diode includes: a semiconductor epitaxial structure including a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, an active layer disposed between the first and second semiconductor layers; a first electrode electrically coupled to the first semiconductor layer; and a second electrode disposed over and electrically coupled to said second semiconductor layer; wherein: the first electrode includes a plurality of first sub-electrodes; the second electrode includes a plurality of second sub-electrodes; and any two adjacent first sub-electrodes and/or second sub-electrodes have a same projection distance.

Abstract: A high-voltage light emitting diode and fabrication method thereof, in which, the liquid insulating material layer/the liquid conducting material layer, after curing, is used for insulating/connecting, making the isolated groove between the light emitting units extremely narrow (opening width ?0.4 ?m, such as ?0.3 ?m), which improves single chip output, expands effective light emitting region area and improves light emitting efficiency; the serial/parallel connection yield is improved for this method avoids easy disconnection of wires across a groove with extremely large height difference in conventional high-voltage light emitting diodes; in addition, the manufacturing cost is reduced for the LED can be directly fabricated at the chip fabrication end.

Abstract: A light-emitting diode includes: a semiconductor epitaxial structure including a first semiconductor layer, a second semiconductor layer disposed over the first semiconductor layer, an active layer disposed between the first and second semiconductor layers; a first electrode electrically coupled to the first semiconductor layer; and a second electrode disposed over and electrically coupled to said second semiconductor layer; wherein: the first electrode includes a plurality of first sub-electrodes; the second electrode includes a plurality of second sub-electrodes; and any two adjacent first sub-electrodes and/or second sub-electrodes have a same projection distance.

Abstract: A high-voltage light emitting diode and fabrication method thereof, in which, the liquid insulating material layer/the liquid conducting material layer, after curing, is used for insulating/connecting, making the isolated groove between the light emitting units extremely narrow (opening width?0.4 ?m, such as ?0.3 ?m), which improves single chip output, expands effective light emitting region area and improves light emitting efficiency; the serial/parallel connection yield is improved for this method avoids easy disconnection of wires across a groove with extremely large height difference in conventional high-voltage light emitting diodes; in addition, the manufacturing cost is reduced for the LED can be directly fabricated at the chip fabrication end.

Abstract: A method for manufacturing the AlGaInP LED having a vertical structure is provided, including: growing, epitaxially, a buffer layer, an n-type contact layer, an n-type textured layer, a confined layer, an active layer, a p-type confined layer and a p-type window layer in that order on a temporary substrate, to form a texturable epitaxial layer; forming a transparent conducting film with periodicity on the p-type window layer of the epitaxial layer, forming a regulated through-hole on the transparent conducting film, and filling the through-hole with a conducting material; forming a total-reflection metal layer on the transparent conducting film; bonding a permanent substrate with the texturable epitaxial layer via a bonding layer, and bring the total-reflection metal layer into contact with the bonding layer; removing the temporary substrate and the buffer layer; forming an n-type extension electrode on the exposed n-type contact layer; removing the n-type contact layer, and forming a pad on the n-type textur

Abstract: A method for manufacturing the AlGaInP LED having a vertical structure is provided, including: growing, epitaxially, a buffer layer, an n-type contact layer, an n-type textured layer, a confined layer, an active layer, a p-type confined layer and a p-type window layer in that order on a temporary substrate, to form a texturable epitaxial layer; forming a transparent conducting film with periodicity on the p-type window layer of the epitaxial layer, forming a regulated through-hole on the transparent conducting film, and filling the through-hole with a conducting material; forming a total-reflection metal layer on the transparent conducting film; bonding a permanent substrate with the texturable epitaxial layer via a bonding layer, and bring the total-reflection metal layer into contact with the bonding layer; removing the temporary substrate and the buffer layer; forming an n-type extension electrode on the exposed n-type contact layer; removing the n-type contact layer, and forming a pad on the n-type textur

Abstract: A method of forming a selective area semiconductor compound epitaxy layer is provided. The method includes the step of using two silicon-containing precursors as gas source for implementing a process of manufacturing the selective area semiconductor compound epitaxy layer, so as to form a semiconductor compound epitaxy layer on an exposed monocrystalline silicon region of a substrate.