Abstract: Substrate treatment apparatus, printers, and methods to treat a print substrate are disclosed. An example apparatus includes a first roller to receive a treatment fluid from a reservoir, a blade to adjust an amount of the treatment fluid present on the first roller, and a second roller to receive an adjusted amount of the treatment fluid from the first roller and to apply the treatment fluid to a substrate, the treatment fluid applied to the substrate to result in a layer of treatment fluid less than about 0.4 micrometers thick on the substrate.

Abstract: Contact printing can be used to form electrically active micro-features on a substrate. An ink formulation containing an oxide precursor is used to form the micro-features, which are heat cured to form oxides. Various precursors are illustrated which can be used to form conducting, insulating, and semiconductor micro-features.

Abstract: A fabrication process, including forming one or more layers on at least a sidewall of a topographical feature of a substantially planar substrate, the sidewall being substantially orthogonal to the substrate; and planarizing respective portions of the one or more layers to form a planar surface substantially parallel to the substrate, wherein the planar surface includes respective co-planar surfaces of the one or more layers, at least one of the surfaces having a dimension determined by a thickness of the corresponding layer.

Abstract: Contact printing can be used to form electrically active micro-features on a substrate. An ink formulation containing an oxide precursor is used to form the micro-features, which are heat cured to form oxides. Various precursors are illustrated which can be used to form conducting, insulating, and semiconductor micro-features.

Abstract: A method for fabricating an electrical interconnect between two or more electrical components. A conductive layer is provided on a substarte and a thin, patterned catalyst array is deposited on an exposed surface of the conductive layer. A gas or vapor of a metallic precursor of a metal nanowire (MeNW) is provided around the catalyst array, and MeNWs grow between the conductive layer and the catalyst array. The catalyst array and a portion of each of the MeNWs are removed to provide exposed ends of the MeNWs.

Abstract: An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited copper metal plug. An encapsulating metal deposit caps the plug without any intervening oxidation and degradation. In a transition from copper to a codeposit of copper, an encapsulating Pt, Pd, and/or Ag metal deposits in the electroless bath without oxidation and degradation followed by a pure deposit of the encapsulating metal layer to cap the plug.

Abstract: An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited copper metal plug. An encapsulating metal deposit caps the plug without any intervening oxidation and degradation. In a transition from copper to a codeposit of copper, an encapsulating Pt, Pd, and/or Ag metal deposits in the electroless bath without oxidation and degradation followed by a pure deposit of the encapsulating metal layer to cap the plug.

Abstract: A novel method for the activation of semiconductor substrates for highly selective electroless copper plating in multilayer interconnect metallization lines and vias/contact holes has been developed. A copper-seeded polysilicon layer is provided over the substrate to facilitate growth of copper into the vias. Subsequent rinsing and chemical-mechanical polishing processes allow removal of overgrowth of copper and the polysilicon layer to achieve overall smooth topography of the copper surface and the insulating layer surface of the substrate.

Abstract: A method of for electroless copper deposition using a Pd/Pd acetate seeding layer formed in using only two components (Pd acetate and solvent) to form an interconnect for a semiconductor device. The invention has two preferred embodiments. The first embodiment forms a Key seed layer composed of Pd/Pd acetate by a spin-on or dip process for the electroless plating of a Cu plug. The second embodiment forms a Pd passivation cap layer over the Cu plug to prevent the Cu plug from oxidizing.

Abstract: A method for forming uniform ultrathin silicide features in the fabrication of an integrated circuit is described. A metal layer is deposited over the surface of a silicon semiconductor substrate. An array of heated metallic tips contact the metal layer whereby the metal layer is transformed to a metal silicide where it is contacted by the metallic tips and wherein the metal layer not contacted by the metallic tips is unreacted. The unreacted metal layer is removed leaving the metal silicide as uniform ultrathin silicide features. Alternatively, a metal acetate layer is spin-coated over the surface of a silicon semiconductor substrate. An array of heated metallic tips contacts the metal acetate layer whereby the metal acetate layer is transformed to a metal silicide where the metallic tips contact the metal acetate layer and wherein the metal acetate slayer not contacted by the metallic tips is unreacted.

Abstract: An encapsulated copper plug on a doped silicon semiconductor substrate has a substrate surface, covered with insulation, with a plug hole with a diffusion barrier formed on the walls and the bottom of the hole to the top of the hole. The plug hole is partially filled with an electrolessly deposited copper metal plug. An encapsulating metal deposit caps the plug without any intervening oxidation and degradation. In a transition from copper to a codeposit of copper, an encapsulating Pt, Pd, and/or Ag metal deposits in the electroless bath without oxidation and degradation followed by a pure deposit of the encapsulating metal layer to cap the plug.

Abstract: The present invention provides a high precision three-dimensional alignment system using SPM techniques and method of using the same. The system comprises a fine distance control unit for the effective three-dimensional micromovement in the nanometer range of a planar object, and proximity detection unit to monitor the alignment process. In the preferred embodiment, the fine distance control unit comprises a set of at least three strategically positioned fine distance control elements which are capable of controlled expansion and contraction in the nanometer range. The most preferred embodiment of the fine distance control element comprises a piezoelectric tube, which crystal size may be varied by varying an applied voltage. This system may be applied to microlithography, in which case the planar object is a scribing tool having a planar base with multiple tips fabricated on one surface.

Abstract: An improved and new method for fabricating conducting vias between successive layers of conductive interconnection patterns in a semiconductor integrated circuit has been developed. The method utilizes a first CMP step to form a barrier lined contact hole, deposition of copper by electroless plating into the barrier lined contact hole, and a second CMP step to remove overgrowth of copper, thus producing coplanarity between the copper surface and the surrounding insulator surface.