Abstract: A data processing apparatus includes pointer storage configured to store pointer values for pointers. Increment circuitry, responsive to one or more increment events, increments each of the pointer values in dependence on a corresponding live pointer value update condition from corresponding live pointer value update conditions. The corresponding live pointer value update condition is different for each of the pointers. History storage circuitry stores resolved behaviours of instances of a control flow instruction, each of the resolved behaviours being associated with one of the pointers. At least one of the live pointer value update conditions is changeable at runtime. Consequently, storage can be reduced as compared to a situation where all pointer value update conditions are active.

Abstract: A data processing apparatus is provided. It includes first history storage circuitry that stores control flow information of control flow instructions. Second history storage circuitry stores a subset of the control flow information by considering a subset of the control flow instructions. Prediction circuitry produces a prediction for a specific one of the control flow instructions based on the subset of the control flow information and power control circuitry performs a determination of an extent to which the subset of the control flow information matches the control flow information and disables the prediction circuitry in dependence on a result of the determination.

Abstract: A data processing apparatus is provided. It includes history storage circuitry that stores historic data of instructions and prediction circuitry that predicts a historic datum of a specific instruction based on subsets of the historic data of the instructions. The history storage circuitry overwrites the historic data of one of the instructions to form a corrupted instruction datum and at least one of the subsets of the historic data of the instructions includes the corrupted historic datum.

Abstract: An apparatus stores pointer values for pointers which are incremented differentially and has prediction circuitry to maintain prediction entries each identifying a control flow instruction, an associated pointer, and a behaviour record indicating resolved behaviour of the control flow instruction. Resolved behaviour stored in a selected element of the behaviour record identified using a pointer value of the associated pointer may be used as predicted behaviour for a control flow instruction. The prediction entries include a first type of prediction entry and a further type of prediction entry, where prediction circuitry uses each prediction entry of the first type to identify a control flow instruction whose associated pointer is within a first subset of the pointers, and uses each prediction entry of a further type to identify a control flow instruction whose associated pointer is within a further subset of the pointers excluding at least one pointer of the first subset.

Abstract: An apparatus has pointer storage to store pointer values for a plurality of pointers and increment circuitry, responsive to a series of increment events, to differentially increment the pointer values of the pointers. Training circuitry comprises tracker circuitry to maintain a plurality of tracker entries and cache circuitry to maintain a plurality of cache entries. Each tracker entry identifies a control flow instruction, and each cache entry stores a resolved behaviour of an instance of a control flow instruction identified by a tracker entry. For a given control flow instruction identified in a given tracker entry, the training circuitry performs a training process to seek to determine, as an associated pointer for the given control flow instruction, a pointer from amongst the plurality of pointers whose pointer value increments in a manner that meets a correlation threshold with occurrence of instances of the given control flow instruction.

Abstract: Combiner circuitry generates a combined prediction associated with a given address based on combining respective sets of prediction information generated by two or more predictors. Predictor control circuitry determines, based on a lookup of a prediction input address in a combiner hint data structure, whether a second predictor lookup suppression condition is satisfied for the prediction input address indicating that the combined prediction that would be determined by the combiner circuitry for the prediction input address is likely to be derivable from a prediction outcome predicted by the first predictor for the prediction input address. If this condition is satisfied, a lookup of the second predictor is suppressed and the prediction associated with the prediction input address is generated based on the prediction outcome predicted by the first predictor for the prediction input address.

Abstract: Prediction circuitry generates a prediction associated with a prediction input address, for controlling a speculative action by a processor. The prediction circuitry comprises combiner circuitry to determine a combined prediction by applying a prediction combination function to a given address and sets of prediction information generated by a plurality of predictors corresponding to the given address. A combiner cache structure comprises combiner cache entries. A given combiner cache entry associated with an address indication indicates items of combined prediction information determined by the combiner circuitry for an address corresponding to the address indication and different combinations of possible values for the respective sets of prediction information.

Abstract: An apparatus has a data storage structure to store data items tagged by respective tag values and stores, in association with each data item, a respective tag group identifier to identify other data items having a same tag value within a collection of data items. The apparatus also has tag match circuitry to identify one or more hitting data items. Prioritisation circuitry is provided to select candidate data items which, relative to any other data items in the particular collection of data items having the same tag group identifier as the selected candidate data item is favoured according to an ordering of the data items. The prioritisation circuitry selects the one or more candidate data items before the identification of the hitting data items is available from the tag match circuitry. Data item selection circuitry selects a candidate data item for which the tag match circuitry detected a match.

Abstract: An apparatus is provided having pointer storage to store pointer values for a plurality of pointers, with the pointer values of the pointers being differentially incremented in response to a series of increment events. Tracker circuitry maintains a plurality of tracker entries, each tracker entry identifying a control flow instruction and a current active pointer (from amongst the pointers) to be associated with that control flow instruction. Cache circuitry maintains a plurality of cache entries, each cache entry storing a resolved behaviour of an instance of a control flow instruction identified by a tracker entry along with an associated tag value generated when the resolved behaviour was allocated into that cache entry. For a given entry the associated tag value may be generated in dependence on an address indication of the control flow instruction whose resolved behaviour is being stored in that entry and the current active pointer associated with that control flow instruction.

Abstract: An apparatus is provided having pointer storage to store pointer values for a plurality of pointers, with the pointer values of the pointers being differentially incremented in response to a series of increment events. Tracker circuitry maintains a plurality of tracker entries, each tracker entry identifying a control flow instruction and a current active pointer (from amongst the pointers) to be associated with that control flow instruction. Cache circuitry maintains a plurality of cache entries, each cache entry storing a resolved behaviour of an instance of a control flow instruction identified by a tracker entry along with an associated tag value generated when the resolved behaviour was allocated into that cache entry. For a given entry the associated tag value may be generated in dependence on an address indication of the control flow instruction whose resolved behaviour is being stored in that entry and the current active pointer associated with that control flow instruction.

Abstract: Instruction information generation circuitry generates instruction information. Instruction information storage circuitry comprises a plurality of elements having physical sub-elements configured to temporarily store units of instruction information. Allocation circuitry is configured to receive, from the instruction information generation circuitry, given instruction information. It determines a mapping of a plurality of ordered virtual sub-elements, such that each virtual sub-element maps onto a respective one of said physical sub-elements. The given instruction information is stored into the virtual sub-elements of a given element, according to the mapping, such that at least one virtual sub-element lower in said order has a higher priority than at least one virtual sub-element higher in said order. Sub-element deactivation circuitry is configured to track usage of said virtual sub-elements across the plurality of elements and adaptively deactivate virtual sub-elements.

Abstract: An apparatus has a data storage structure to store data items tagged by respective tag values and stores, in association with each data item, a respective tag group identifier to identify other data items having a same tag value within a collection of data items. The apparatus also has tag match circuitry to identify one or more hitting data items. Prioritisation circuitry is provided to select candidate data items which, relative to any other data items in the particular collection of data items having the same tag group identifier as the selected candidate data item is favoured according to an ordering of the data items. The prioritisation circuitry selects the one or more candidate data items before the identification of the hitting data items is available from the tag match circuitry. Data item selection circuitry selects a candidate data item for which the tag match circuitry detected a match.

Abstract: There is provided a data processing apparatus comprising history storage circuitry that stores sets of behaviours of helper instructions for a control flow instruction. Pointer storage circuitry stores pointers, each associated with one of the sets. The behaviours in the one of the sets are indexed according to one of the pointers associated with that one of the sets. Increment circuitry increments at least some of the pointers in response to an increment event and prediction circuitry determines a predicted behaviour of the control flow instruction using one of the sets of behaviours.

Abstract: Processing circuitry performs processing operations in response to micro-operations. Front end circuitry supplies the micro-operations to be processed by the processing circuitry. Prediction circuitry generates a prediction of a number of loop iterations for which one or more micro-operations per loop iteration are to be supplied by the front end circuitry, where an actual number of loop iterations to be processed by the processing circuitry is resolvable by the processing circuitry based on at least one operand corresponding to a first loop iteration to be processed by the processing circuitry. The front end circuitry varies, based on a level of confidence in the prediction of the number of loop iterations, a supply rate with which the one or more micro-operations for at least a subset of the loop iterations are supplied to the processing circuitry.

Abstract: A data processing apparatus provides predictions for hard to predict instructions. Prediction circuitry generates predictions relating to predictable instructions in a stream and stores, with respect to each of the predictable instructions, a reference to a set of monitored instructions in the stream to be used for generating predictions for the predictable instructions. Processing circuitry executes the predictable instructions in the stream using the predictions. A given correlation parameter is stored between a given predictable instruction in the stream and a subset of the set of monitored instructions of the given predictable instruction to assist in generating the predictions. If the given correlation parameter is currently stored, the prediction circuitry generates a given prediction relating to the given predictable instruction based on the subset of the set of monitored instructions.

Abstract: A data processing apparatus is provided that includes bimodal control flow prediction circuitry for performing a prediction of whether a conditional control flow instruction will be taken. Storage circuitry stores, in association with the control flow instruction, a stored state of the data processing apparatus and reversal circuitry reverses the prediction in dependence on the stored state of the data processing apparatus corresponding with a current state of the data processing apparatus when execution of the control flow instruction is to be performed.

Abstract: Aspects of the present disclosure relate to an apparatus comprising prediction circuitry having a plurality of hierarchical prediction units to perform respective hierarchical predictions of instructions for execution, wherein predictions higher in the hierarchy have a higher expected accuracy than predictions lower in the hierarchy. Responsive to a given prediction higher in the hierarchy being different to a corresponding prediction lower in the hierarchy, the corresponding prediction lower in the hierarchy is corrected. A prediction correction metric determination unit determines a prediction correction metric indicative of an incidence of uncorrected predictions performed by the prediction circuitry. Fetch circuitry fetches instructions predicted by at least one of said plurality of hierarchical predictions, and delays said fetching based on the prediction correction metric indicating an incidence of uncorrected predictions below a threshold.

Abstract: A first type of prediction, for controlling execution of at least one instruction by processing circuitry, is based at least on a first prediction table storing prediction information looked up based on at least a first portion of branch history information stored in branch history storage corresponding to a first predetermined number of branches. In response to detecting an execution state switch of the processing circuitry from a first execution state to a second, more privileged, execution state, use of the first prediction table for determining the first type of prediction is disabled. In response to detecting that a number of branches causing an update to the branch history storage since the execution state switch is greater than or equal to the first predetermined number, use of the first prediction table in determining the first type of prediction is re-enabled.

Abstract: There is provided a data processing apparatus comprising history storage circuitry that stores sets of behaviours of helper instructions for a control flow instruction. Pointer storage circuitry stores pointers, each associated with one of the sets. The behaviours in the one of the sets are indexed according to one of the pointers associated with that one of the sets. Increment circuitry increments at least some of the pointers in response to an increment event and prediction circuitry determines a predicted behaviour of the control flow instruction using one of the sets of behaviours.

Abstract: Prediction circuitry predicts a number of iterations of a fetching process to be performed to control fetching of data/instructions for processing operations that are predicted to be performed by processing circuitry. The processing circuitry can tolerate performing unnecessary iterations of the fetching process following an over-prediction of the number of iterations. In response to the processing circuitry resolving an actual number of iterations, the prediction circuitry adjusts the prediction state information used to predict the number of iterations, based on whether a first predicted number of iterations, predicted based on a first iteration prediction parameter, provides a good prediction (when the first predicted number of iterations is in a range i_cnt to i_cnt+N, where i_cnt is the actual number of iterations and N?1), or a misprediction (when the first predicted number of iterations is outside the range i_cnt to i_cnt+N).