Abstract: An electronic control unit for controlling and/or regulating at least one motor vehicle includes at least one integrated microcontroller system for executing software and at least two microcontroller units that each executes at least one independent operating system. The at least one interface is provided for the purpose of interchanging information between the microcontroller units. The electronic control unit includes a first microcontroller unit configured to control and/or regulate of a first motor vehicle system, and a second microcontroller unit configured to use the interface of the first microcontroller unit to provide defaults for the control and/or regulation of the first motor vehicle system.

Abstract: An electronic control unit for controlling and/or regulating at least one motor vehicle includes at least one integrated microcontroller system for executing software and at least two microcontroller units that each executes at least one independent operating system. The at least one interface is provided for the purpose of interchanging information between the microcontroller units.

Abstract: A memory mapping system is connectable to a multi-processing arrangement. The multi-processing arrangement includes a first processing unit and a second processing unit. The memory mapping system includes a main memory to which the second processing unit does not have write access, the main memory including a first memory section and a second memory section. An associated memory is associated with the second memory section. The associated memory includes a memory section to which the second processing unit has write access. A consistency control unit can maintaining consistency between data stored in the associated memory and data stored in the second memory section.

Abstract: A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or subaddress is represented by additional address bit lines, the actually accessed address/subaddress is recovered using the address bit lines, and the actually selected address/subaddress is compared with the applied address/subaddress, obtained from the additional address bit lines, in order to recognize an error in the addressing circuit.

Abstract: A memory mapping system is connectable to a multi-processing arrangement. The multi-processing arrangement includes a first processing unit and a second processing unit. The memory mapping system includes a main memory to which the second processing unit does not have write access, the main memory including a first memory section and a second memory section. An associated memory is associated with the second memory section. The associated memory includes a memory section to which the second processing unit has write access. A consistency control unit can maintaining consistency between data stored in the associated memory and data stored in the second memory section.

Abstract: A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or subaddress is represented by additional address bit lines, the actually accessed address/subaddress is recovered using the address bit lines, and the actually selected address/subaddress is compared with the applied address/subaddress, obtained from the additional address bit lines, in order to recognize an error in the addressing circuit.