Abstract: Circuitry and associated method for resetting a memory storage cell without a dedicated write cycle therefor. Preferably, the storage cell is provided as part of an age_array employed for monitoring the usage of a Content Addressable Memory (CAM). When a match between search data and contents of a particular location of the CAM is found, a Match signal is generated to set a memory storage cell (referred to as an age_cell) corresponding to the particular CAM location. When the age_array is read, the wordline associated with the age_cell is driven high. Upon developing a voltage separation between the data and data bar nodes of the age_cell, a sense amp senses the data value on the corresponding bit and bit bar lines coupled thereto. A suitable data out signal is generated for outputting the sensed data. Also, a reset control signal is generated to indicate that the read operation is substantially complete with respect to that age_cell.

Abstract: A row and column accessible memory having a plurality of memory cells organized as an array of N rows and N columns with a built-in multiplex. A control logic block and decoder block are operable to effectuate either a row access operation for accessing a selected row or a column access operation for accessing a selected column based on a plurality of address signals supplied to the memory. Each memory cell is provided with a first pair of read and write ports for effectuating the row access operations (controlled through row read wordline select and row write wordline select signals, respectively) and a second pair of read and write ports for effectuating the column access operations (controlled through column read wordline select and column write wordline select signals, respectively). A single I/O block is utilized for sensing and data I/O operations, which requires less silicon area and avoids extra routing required in the conventional solutions.