Abstract: A method for manufacturing semiconductor device is provided. First, a substrate is provided. Then, a plurality of first gate lines disposed in parallel to each other and a first dummy gate line disposed in a direction perpendicular to the first gate lines are formed on the substrate. There is a first gap between the first dummy gate line and the first gate lines and there is a second gap between every pair of adjacent first gate lines. Thereafter, a second composite layer and a conductive layer are sequentially formed over the substrate. The conductive layer is etched back to form a plurality of second device structures that completely fills the second gaps. Then, the conductive layer in the first gap is removed.

Abstract: A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the first memory units are filled with a doped polysilicon layer. Thereafter, a portion of the doped polysilicon layer is removed to form trenches. After that, a metallic layer fills the trenches. A portion of the metallic layer is removed to form a plurality of gates. The gates and the composite layer together form a plurality of second memory units. The second memory units and the first memory units together constitute a memory cell column. Then, a source region and a drain region are formed in the substrate adjacent to the two sides of the memory cell column.

Abstract: A non-volatile memory and fabricating method thereof are provided. First, a plurality of raised bit lines is formed on the substrate. The raised bit lines are paralleled one another, and extended in the same direction. Then, a charge trap layer is formed on the substrate. Afterwards, a plurality of word lines paralleled to one another is formed on the raised bit lines and filled up the gaps between the raised bit lines. Besides, the word lines are extended in another direction crossed by the direction of the raised bit lines. Because the non-volatile memory adopts design of raised bit lines, dopant diffusion induced by thermal processes of the buried bit lines can be avoided.

Abstract: A fabrication method of a flash memory is provided. The substrate having a cell region and a peripheral circuitry region is provided. A patterned dielectric layer and a patterned conductive layer are formed on the substrate, and isolation structures are formed in the substrate. An inter gate dielectric layer and a poly layer are formed sequentially over the substrate. The poly layer and the inter gate dielectric in peripheral circuitry region are removed. After forming a second conductive layer and a mask layer over substrate, memory cells are formed in the cell region and a gate structure is formed in the peripheral circuitry region. A conductive plug is formed above the gate structure for electrically connecting the second conductive layer. Since the inter gate dielectric layer in the peripheral circuitry region is removed, the fabrication of the conductive plug can be simpler and the process window thereof can be improved.

Abstract: A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the first memory units are filled with a doped polysilicon layer. Thereafter, a portion of the doped polysilicon layer is removed to form trenches. After that, a metallic layer fills the trenches. A portion of the metallic layer is removed to form a plurality of gates. The gates and the composite layer together form a plurality of second memory units. The second memory units and the first memory units together constitute a memory cell column. Then, a source region and a drain region are formed in the substrate adjacent to the two sides of the memory cell column.

Abstract: A method for manufacturing semiconductor device is provided. First, a substrate is provided. Then, a plurality of first gate lines disposed in parallel to each other and a first dummy gate line disposed in a direction perpendicular to the first gate lines are formed on the substrate. There is a first gap between the first dummy gate line and the first gate lines and there is a second gap between every pair of adjacent first gate lines. Thereafter, a second composite layer and a conductive layer are sequentially formed over the substrate. The conductive layer is etched back to form a plurality of second device structures that completely fills the second gaps. Then, the conductive layer in the first gap is removed.

Abstract: A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell includes a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. Then, a plurality of gates is formed in the respective gaps. The gates together with a second composite layer form a plurality of second memory cells. The second memory cells and the first memory cells together constitute a memory cell column. In the meantime, a plurality of gate structures is also formed on the peripheral circuit region. The gates in the gaps and the gates in the peripheral circuit region are formed using the same conductive layers.

Abstract: A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell comprises a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. Then, a plurality of gates is formed in the respective gaps. The gates together with a second composite layer form a plurality of second memory cells. The second memory cells and the first memory cells together constitute a memory cell column. In the meantime, a plurality of gate structures is also formed on the peripheral circuit region. The gates in the gaps and the gates in the peripheral circuit region are fabricated using different conductive layers.

Abstract: A method of fabricating a non-volatile memory includes providing a substrate having a composite dielectric layer, a sacrificial layer and a mask layer sequentially formed thereon. The mask layer is patterned to form a plurality of first openings for exposing a portion of the sacrificial layer. The sacrificial layer exposed by the first openings is removed and a plurality of first gates is formed in the first openings. The mask layer is further removed to form a plurality of second openings between the first gates. An insulating layer is formed on the tops and sidewalls of the first gates. A portion of the sacrificial layer exposed by the second openings is removed and a plurality of second gates is formed in the second openings. The second gates and the first gates embody a memory cell column. Source/region regions are formed in the substrate beside the memory cell column.

Abstract: A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell array. Next, a patterned first inter-layer insulating layer is formed on the substrate to form a first trench and a plurality of second trenches. A conductive layer is formed on the substrate to form a source line in the first trench and conductive lines in the second trenches. A second inter-layer insulating layer is formed on the substrate and then a conductive plug having contact with the drain region is formed in the second inter-layer insulating layer and the first inter-layer insulating layer. Then, a bit line having contact with the conductive plug is formed on the second inter-layer insulating layer.

Abstract: A method of fabricating a non-volatile memory is described. A plurality of first memory units having gaps between each other is formed over a substrate. Insulating spacers are formed on the sidewalls of the first memory units. A composite layer is formed on the substrate and the gaps between the first memory units are filled with a doped polysilicon layer. Thereafter, a portion of the doped polysilicon layer is removed to form trenches. After that, a metallic layer fills the trenches. A portion of the metallic layer is removed to form a plurality of gates. The gates and the composite layer together form a plurality of second memory units. The second memory units and the first memory units together constitute a memory cell column. Then, a source region and a drain region are formed in the substrate adjacent to the two sides of the memory cell column.

Abstract: A non-volatile memory having a plurality of memory units each including a select unit and a memory unit is provided. The select unit is disposed on the substrate. The memory cell is disposed on one sidewall of the select unit and the substrate. The select unit includes a gate disposed on the substrate and a first gate dielectric layer disposed between the gate and the substrate. The memory cell includes a pair of floating gate disposed on the substrate, a control gate disposed on the upper surface of the floating gates, an inter-gate dielectric layer disposed between the floating gate and the control gate, a tunneling dielectric layer disposed between the floating gate and the substrate and a second gate dielectric layer disposed between the bottom of the control gate and the substrate.

Abstract: A non-volatile memory having a plurality of memory units is provided. Each memory unit includes a first memory cell and a second memory cell. The first memory cell is disposed on the substrate. The second memory cell is disposed on one sidewall of the first memory cell and the substrate. The first memory cell includes a first control gate disposed on the substrate and a composite layer disposed between the first control gate and the substrate. The second memory cell includes a pair of floating gates disposed on the substrate, a second control gate disposed on the upper surface of the two floating gates, an inter-gate dielectric layer disposed between the floating gate and the second control gate, a tunneling dielectric layer disposed between the floating gate and the substrate and a gate dielectric layer disposed between the bottom of the second control gate and the substrate.

Abstract: A process of fabricating a deep trench capacitor includes the steps of: depositing a nitride masking layer over a substrate; removing portions of the nitride masking layer and substrate to form an exposed deep trench having sidewalls and a bottom surface; forming an oxide fill plug to fill a bottom portion of the trench; removing the oxide fill plug from the trench; doping a region of the substrate enveloping the bottom portion of the trench; depositing a spacer insulating layer over the sidewalls and bottom surface of the trench; removing a portion of the spacer insulating layer to expose a central portion of the bottom surface of the trench; depositing a conducting layer over the spacer insulating layer, and the exposed central portion of the bottom surface, the conducting layer and the doped region of the substrate being in electrical contact and forming a first plate of the capacitor; removing a portion of the conducting layer; removing the spacer insulating layer to expose outer walls of the conducting l

Abstract: The present invention discloses a method for forming a self-aligned contact. In the present invention, a amorphous SiC layer or a HexaChloroDisilane-SiN (HCD-SiN) layer is formed on the surface of a transistor as an etching stopper layer. After removing part of the etching stopper layer, a gate protection film is formed on the surface of the gate electrode of a transistor. Due to the high etching selectivity of the gate protection film to the dielectric layer, the gate protection film effectively prevents the gate electrode of a transistor from being etched in the contact-etching process. In addition, the gate protection film has a low dielectric constant thereby reducing the parasitic capacitance of a bit line formed by the self-aligned contact forming method according to the present invention.

Abstract: The present invention provides a method of forming trench capacitor with a sacrificial silicon nitride. A deep trench structure is formed in a substrate. A TEOS oxide layer is formed on the substrate and filled in said trench region, etched to a first level subsequently, wherein a portion of the TEOS oxide layer is remained in the trench region and a portion of the substrate exposed to form a trench sidewall. A thermally oxidation process is performed to form a collar oxide on the exposed substrate. A silicon nitride sidewall is formed on the collar oxide, then removing the residual TEOS oxide layer by wet etching. The trench region is then etched using the silicon nitride sidewall as a barrier to form a bottle shape trench region for increasing the surface of the trench region. A bottom cell plate is formed in the fresh trench region. The silicon nitride sidewall is removed.

Abstract: A method of fabricating a trench capacitor having high capacitance for ULSI technology below the sub-micrometer scale is provided. The method includes: form a trench on a semiconductor substrate. The trench has a bottom portion and at least one sidewall on the semiconductor substrate. Then, form a diffusion layer in the silicon substrate for circumscribing the bottom portion of the trench and a predetermined region of its sidewall. After that, form a first polysilicon layer on the bottom portion of the trench and in a manner that a portion of the first polysilicon layer does not contact with the sidewall. Then, form a first dielectric layer to completely cover the first polysilicon layer and the diffusion layer. Then, form an upper electrode layer on top of the trench to at least completely cover the first dielectric layer. Eventually, the contact area between the diffusion layer and the dielectric layer has been largely increased so as to maintain sufficient capacitance.

Abstract: A method of forming a DRAM cell with a trench capacitor over a semiconductor substrate comprises the following steps. First, an etching step is performed to form a trench structure in the substrate, wherein the trench structure has a bottom and sidewalls, and the sidewalls are adjacent to the bottom. Then, the trench structure is doped to form a doping region on the bottom and a portion of the sidewalls. A selective etching step is performed to remove a portion of the doping region, wherein a selectivity of the doping region is higher than that of undoped sidewalls. A dielectric layer is formed on a top surface of the trench structure. A conducting layer is then formed in the trench structure. Next, a gate structure is formed on the substrate. A doping step is used to form the drain/source structures adjacent to the gate. A strap region is formed to couple the conducting layer and the drain/source structures.

Abstract: The invention has disclosed a method for forming a multi-cylinder capacitor with simplified steps. First, first and second insulating layers are sequentially formed on a semiconductor substrate. Next, an alternate polysilicon layer is deposited. The alternate polysilicon layer includes a plurality of undoped polysilicon films alternating with a plurality of doped polysilicon films. Thereafter, a portion of said plurality of doped polysilicon films is selectively etched by utilizing the etching selectivity between said plurality of undoped and doped polysilicon films. Finally, the second insulating layer is removed and the undoped polysilicon films are doped to form multi-cylinder electrodes. According to the invention, the reliability of the multi-cylinder capacitor is improved and the cost of production is reduced. In addition, it is not necessary to add other steps if the number of cylindrical electrodes increases.

Abstract: The present invention provides a new method which increases the surface area of the storage node of the capacitor, the method comprising: (1) Forming a photo resistor layer with a circular hole on the surface of the semiconductor wafer; (2) Using a wet isotropic etching method to form a bowl-like shallow concavity (pit) through the hole with a radius bigger than the hole; (3) Using a dry anisotropic etching process to etch a shallow pit through the hole in the central part of the bottom of the shallow pit down through the substrate of the semiconductor wafer; and (4) Eliminating the photo resistor layer, and then depositing a doped polysilicon layer over the shallow pit and the well resulting in a recess corresponding to the shallow pit and the well, wherein the deposition layer with a recess forms the storage node of a capacitor, the storage node having a recess with a larger surface area.