Patents by Inventor Hounien Chen
Hounien Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9336893Abstract: A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.Type: GrantFiled: July 1, 2015Date of Patent: May 10, 2016Assignee: Integrated Silicon Solution, Inc.Inventors: Jong Sang Lee, Hounien Chen, Kyoung Chon Jin
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Publication number: 20150380101Abstract: A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.Type: ApplicationFiled: July 1, 2015Publication date: December 31, 2015Inventors: Jong Sang Lee, Hounien Chen, Kyoung Chon Jin
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Patent number: 9099192Abstract: A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.Type: GrantFiled: January 13, 2014Date of Patent: August 4, 2015Assignee: Integrated Silicon Solution, Inc.Inventors: Jong Sang Lee, Hounien Chen, Kyoung Chon Jin
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Publication number: 20150200018Abstract: A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.Type: ApplicationFiled: January 13, 2014Publication date: July 16, 2015Applicant: Integrated Silicon Solution, Inc.Inventors: Jong Sang Lee, Hounien Chen, Kyoung Chon Jin
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Patent number: 8107294Abstract: A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed.Type: GrantFiled: March 24, 2010Date of Patent: January 31, 2012Assignee: Spansion LLCInventors: Hounien Chen, Nancy S. Leong
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Publication number: 20100177568Abstract: A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed.Type: ApplicationFiled: March 24, 2010Publication date: July 15, 2010Applicant: SPANSION LLCInventors: Hounien CHEN, Nancy S. LEONG
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Patent number: 7706183Abstract: A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed.Type: GrantFiled: July 27, 2005Date of Patent: April 27, 2010Assignee: Spansion LLCInventors: Hounien Chen, Nancy S. Leong
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Patent number: 7453724Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.Type: GrantFiled: October 31, 2007Date of Patent: November 18, 2008Assignee: Spansion, LLCInventors: Aaron Lee, Hounien Chen, Sachit Chandra, Nancy Leong, Guowei Wang
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Patent number: 7433228Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.Type: GrantFiled: September 20, 2005Date of Patent: October 7, 2008Assignee: Spansion LLCInventors: Tiao-Hua Kuo, Nancy Leong, Hounien Chen, Sachit Chandra, Nian Yang
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Patent number: 7423915Abstract: A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.Type: GrantFiled: January 17, 2006Date of Patent: September 9, 2008Assignee: Spansion LLCInventors: Nancy Leong, Sachit Chandra, Hounien Chen
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Patent number: 7342830Abstract: A method for programming a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes performing a program operation on a group of memory cells, where the group of memory cells includes a plurality of subgroups. A verify status value is stored for each subgroup, the verify status value indicating a verify status of each subgroup, wherein the verify status value indicates whether an associated subgroup has been program verified. A program verify operation is performed on a selected subgroup when the verify status value associated with the selected subgroup indicates that the selected verify subgroup has not been program verified.Type: GrantFiled: January 17, 2006Date of Patent: March 11, 2008Assignee: Spansion LLCInventors: Hounien Chen, Nancy S. Leong
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Publication number: 20080049516Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.Type: ApplicationFiled: October 31, 2007Publication date: February 28, 2008Applicant: SPANSION L.L.C.Inventors: Aaron LEE, Hounien CHEN, Sachit CHANDRA, Nancy LEONG, Guowei WANG
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Patent number: 7307878Abstract: A method is provided for programming a nonvolatile memory device including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window that identifies a plurality of memory cells in the array. A first group of memory cells to be programmed is identified from the plurality of memory cells in the programming window. The first group of memory cells is programmed and a programming state of the first group of memory cells is verified.Type: GrantFiled: August 29, 2005Date of Patent: December 11, 2007Assignee: Spansion LLCInventors: Aaron Lee, Hounien Chen, Sachit Chandra, Nancy Leong, Guowei Wang
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Publication number: 20070165458Abstract: A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.Type: ApplicationFiled: January 17, 2006Publication date: July 19, 2007Inventors: Nancy Leong, Sachit Chandra, Hounien Chen
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Publication number: 20070076513Abstract: A decoder system for a memory device includes a high voltage pump, a high voltage switch, and a loading capacitor. The high voltage pump generates a boost voltage, and the high voltage switch couples one of the boost voltage or a low voltage to a line of the memory device. The loading capacitor is coupled to a node between the high voltage pump and the high voltage switch to minimize voltage dipping of the boost voltage.Type: ApplicationFiled: October 4, 2005Publication date: April 5, 2007Inventors: Nian Yang, Fan Lai, Hounien Chen
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Publication number: 20070064480Abstract: A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.Type: ApplicationFiled: September 20, 2005Publication date: March 22, 2007Inventors: Tiao-Hua Kuo, Nancy Leong, Hounien Chen, Sachit Chandra, Nian Yang
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Publication number: 20070035991Abstract: A method for reading a nonvolatile memory array including an array of memory cells, each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region, includes receiving, at an address register, a read command including an address for a memory cell in the array of memory cells and an indication regarding whether the read command is a full page read command or a partial page read command. A starting address for a page including the received address is identified, wherein the page includes multiple rows of memory cells in the array of memory cells. The address register is reset to the starting address for the page. It is determined whether all memory cells in the page are non-programmed. Data indicative of a non-programmed state of the page is output if it is determined that all memory cells in the page are non-programmed.Type: ApplicationFiled: July 27, 2005Publication date: February 15, 2007Inventors: Hounien Chen, Nancy Leong