Abstract: A read-out circuit and a read-out method for a three-dimensional memory, comprises a read reference circuit and a sensitive amplifier, the read reference circuit produces read reference current capable of quickly distinguishing reading low-resistance state unit current and reading high-resistance state unit current. The read reference circuit comprises a reference unit, a bit line matching module, a word line matching module and a transmission gate parasitic parameter matching module. With respect to the parasitic effect and electric leakage of the three-dimensional memory in the plane and vertical directions, the present invention introduces the matching of bit line parasite parameters, leakage current and transmission gate parasitic parameters into the read reference current, and introduces the matching of parasitic parameters of current mirror into the read current, thereby eliminating the phenomenon of pseudo reading and reducing the read-out time.

Abstract: A read circuit of storage class memory comprises: an array; a read reference circuit, having the same bit line parasitic parameters as the array, having the same read transmission gate parasitic parameters as the array, used to generate a read reference current; a sense amplifier, providing the same current mirror parasitic parameters as the reference side, used to generate a read current from a selected memory cell, compare the said read current with the said read reference current and output a readout result. In the present invention, the said read current and the said read reference current are generated at the same time, the transient curve of the said read reference current is between the low resistance state read current and the high resistance state read current from an early stage. The present invention largely reduces the read access time, has a good process variation tolerance, has a wide application, and is easy to be used in the practical product.

Abstract: A read-out circuit and a read-out method for a three-dimensional memory, comprises a read reference circuit and a sensitive amplifier, the read reference circuit produces read reference current capable of quickly distinguishing reading low-resistance state unit current and reading high-resistance state unit current. The read reference circuit comprises a reference unit, a bit line matching module, a word line matching module and a transmission gate parasitic parameter matching module. With respect to the parasitic effect and electric leakage of the three-dimensional memory in the plane and vertical directions, the present invention introduces the matching of bit line parasite parameters, leakage current and transmission gate parasitic parameters into the read reference current, and introduces the matching of parasitic parameters of current mirror into the read current, thereby eliminating the phenomenon of pseudo reading and reducing the read-out time.

Abstract: A read circuit of storage class memory comprises: an array; a read reference circuit, having the same bit line parasitic parameters as the array, having the same read transmission gate parasitic parameters as the array, used to generate a read reference current; a sense amplifier, providing the same current mirror parasitic parameters as the reference side, used to generate a read current from a selected memory cell, compare the said read current with the said read reference current and output a readout result. In the present invention, the said read current and the said read reference current are generated at the same time, the transient curve of the said read reference current is between the low resistance state read current and the high resistance state read current from an early stage. The present invention largely reduces the read access time, has a good process variation tolerance, has a wide application, and is easy to be used in the practical product.

Abstract: A data readout circuit of phase change memory, relating to one or more phase change memory cells, wherein each phase change memory cell is connected to the control circuit by bit line and word line; said data readout circuit comprises: a clamp voltage generating circuit, used to generate a clamp voltage; a precharge circuit, used to fast charge bit line under the control of a clamp voltage; a clamped current generating circuit, used to generate a clamped current to keep bit line at clamped state under the control of a clamp voltage; a clamped current operation circuit, used to perform subtraction and multiplication on clamped current to increase the difference of clamped current between high resistance state and low resistance state; a sense amplifier circuit, used to compare the operated clamped current and the reference current and output the readout result.

Abstract: A data readout circuit of phase change memory, relating to one or more phase change memory cells, wherein each phase change memory cell is connected to the control circuit by bit line and word line; said data readout circuit comprises: a clamp voltage generating circuit, used to generate a clamp voltage; a precharge circuit, used to fast charge bit line under the control of a clamp voltage; a clamped current generating circuit, used to generate a clamped current to keep bit line at clamped state under the control of a clamp voltage; a clamped current operation circuit, used to perform subtraction and multiplication on clamped current to increase the difference of clamped current between high resistance state and low resistance state; a sense amplifier circuit, used to compare the operated clamped current and the reference current and output the readout result.