Patents by Inventor Houqiang Fu
Houqiang Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11626483Abstract: Fabricating a regrown GaN p-n junction includes depositing a n-GaN layer on a substrate including n+-GaN, etching a surface of the n-GaN layer to yield an etched surface, depositing a p-GaN layer on the etched surface, etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate, and passivating a portion of the p-GaN layer around an edge of the mesa. The regrown GaN p-n junction is defined at an interface between the n-GaN layer and the p-GaN layer. The regrown GaN p-n junction includes a substrate, a n-GaN layer on the substrate having an etched surface, a p-GaN layer on the etched surface, a mesa defined by an etched portion of the n-GaN layer and an etched portion of the p-GaN layer, and a passivated portion of the p-GaN layer around an edge of the mesa.Type: GrantFiled: September 24, 2020Date of Patent: April 11, 2023Assignee: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Yuji Zhao, Kai Fu, Houqiang Fu
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Publication number: 20230106300Abstract: Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiO2 hard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiO2 hard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.Type: ApplicationFiled: November 4, 2022Publication date: April 6, 2023Inventors: Yuji Zhao, Chen Yang, Houqiang Fu, Xuanqi Huang, Kai Fu
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Patent number: 11527573Abstract: A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.Type: GrantFiled: March 29, 2021Date of Patent: December 13, 2022Assignee: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Kai Fu, Houqiang Fu, Yuji Zhao
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Patent number: 11495694Abstract: Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiO2 hard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiO2 hard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.Type: GrantFiled: July 12, 2021Date of Patent: November 8, 2022Assignee: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Yuji Zhao, Chen Yang, Houqiang Fu, Xuanqi Huang, Kai Fu
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Patent number: 11417529Abstract: A p-n diode includes a first electrode, a n-GaN layer on the first electrode, a p-GaN layer on the n-GaN layer, and a second electrode on a first portion of the p-GaN layer. A region of the p-GaN layer surrounding the electrode is a passivated region. Treating a GaN power device having a p-GaN layer includes covering a portion of the p-GaN layer with a metal layer, exposing the p-GaN layer to a hydrogen plasma, and thermally annealing the p-GaN layer, thereby passivating a region of the p-GaN layer proximate the metal layer.Type: GrantFiled: October 16, 2020Date of Patent: August 16, 2022Assignee: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Yuji Zhao, Houqiang Fu, Kai Fu
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Publication number: 20220013671Abstract: Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiO2 hard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiO2 hard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.Type: ApplicationFiled: July 12, 2021Publication date: January 13, 2022Inventors: Yuji Zhao, Chen Yang, Houqiang Fu, Xuanqi Huang, Kai Fu
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Publication number: 20210242281Abstract: A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.Type: ApplicationFiled: March 29, 2021Publication date: August 5, 2021Inventors: Kai Fu, Houqiang Fu, Yuji Zhao
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Publication number: 20210202257Abstract: A p-n diode includes a first electrode, a n-GaN layer on the first electrode, a p-GaN layer on the n-GaN layer, and a second electrode on a first portion of the p-GaN layer. A region of the p-GaN layer surrounding the electrode is a passivated region. Treating a GaN power device having a p-GaN layer includes covering a portion of the p-GaN layer with a metal layer, exposing the p-GaN layer to a hydrogen plasma, and thermally annealing the p-GaN layer, thereby passivating a region of the p-GaN layer proximate the metal layer.Type: ApplicationFiled: October 16, 2020Publication date: July 1, 2021Inventors: Yuji Zhao, Houqiang Fu, Kai Fu
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Publication number: 20210104603Abstract: Fabricating a regrown GaN p-n junction includes depositing a n-GaN layer on a substrate including n+-GaN, etching a surface of the n-GaN layer to yield an etched surface, depositing a p-GaN layer on the etched surface, etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate, and passivating a portion of the p-GaN layer around an edge of the mesa. The regrown GaN p-n junction is defined at an interface between the n-GaN layer and the p-GaN layer. The regrown GaN p-n junction includes a substrate, a n-GaN layer on the substrate having an etched surface, a p-GaN layer on the etched surface, a mesa defined by an etched portion of the n-GaN layer and an etched portion of the p-GaN layer, and a passivated portion of the p-GaN layer around an edge of the mesa.Type: ApplicationFiled: September 24, 2020Publication date: April 8, 2021Inventors: Yuji Zhao, Kai Fu, Houqiang Fu
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Patent number: 10964749Abstract: A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.Type: GrantFiled: October 29, 2019Date of Patent: March 30, 2021Assignee: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Kai Fu, Houqiang Fu, Yuji Zhao
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Publication number: 20200295214Abstract: A pn heterojunction diode includes a p-GaN substrate, a layer of ?-Ga2O3 on a surface of the p-GaN substrate, an n contact disposed on a surface of the ?-Ga2O3 layer opposite the p-GaN substrate, and a p contact disposed on the surface of the p-GaN substrate and proximate the GaN substrate. Fabricating a pn heterojunction diode includes depositing a metal on a first surface of a ?-Ga2O3 wafer to form a first contact on the first surface of the ?-Ga2O3 wafer, adhering the first contact to an adhesive material, thereby exposing a second surface of the ?-Ga2O3 wafer, wherein the second surface is opposite the first surface, exfoliating layers of the ?-Ga2O3 wafer from the second surface to yield an exfoliated surface on the ?-Ga2O3 wafer, and contacting the exfoliated surface with a surface of a p-GaN substrate to yield a stack.Type: ApplicationFiled: March 13, 2020Publication date: September 17, 2020Inventors: Jossue Montes, Chen Yang, Houqiang Fu, Jingan Zhou, Yuji Zhao
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Patent number: 10700218Abstract: An AlN Schottky barrier diode device on sapphire substrates is formed using metal organic chemical vapor deposition and demonstrates a kV-level breakdown voltage. The device structure employs a thin n-AlN epilayer as the device active region and thick resistive AlN underlayer as the insulator. At room temperature, the device was characterized by a low turn-on voltage of 1.2 V, a high on/off ratio of ˜105, a low ideality factor of 5.5, and a low reverse leakage current below 1 nA. Due to the ultra-wide bandgap of AlN, the device also exhibited excellent thermal stability over 500 K representing, therefore, a cost-effective route to high performance AlN based Schottky barrier diodes for high power, high voltage and high temperature applications.Type: GrantFiled: November 1, 2018Date of Patent: June 30, 2020Assignee: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Yuji Zhao, Houqiang Fu
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Publication number: 20200144328Abstract: A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.Type: ApplicationFiled: October 29, 2019Publication date: May 7, 2020Inventors: Kai Fu, Houqiang Fu, Yuji Zhao
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Publication number: 20190140110Abstract: An AlN Schottky barrier diode device on sapphire substrates is formed using metal organic chemical vapor deposition and demonstrates a kV-level breakdown voltage. The device structure employs a thin n-AlN epilayer as the device active region and thick resistive AlN underlayer as the insulator. At room temperature, the device was characterized by a low turn-on voltage of 1.2 V, a high on/off ratio of ˜105, a low ideality factor of 5.5, and a low reverse leakage current below 1 nA. Due to the ultra-wide bandgap of AlN, the device also exhibited excellent thermal stability over 500 K representing, therefore, a cost-effective route to high performance AlN based Schottky barrier diodes for high power, high voltage and high temperature applications.Type: ApplicationFiled: November 1, 2018Publication date: May 9, 2019Inventors: Yuji Zhao, Houqiang Fu