Patents by Inventor How Kiat Liew
How Kiat Liew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942369Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: GrantFiled: July 30, 2020Date of Patent: March 26, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh Krishnan, Sw Wei Wang, Ch Chew, How Kiat Liew, Fui Fui Tan
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Publication number: 20240006363Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: ApplicationFiled: September 13, 2023Publication date: January 4, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw WANG, CH CHEW, Eiji KUROSE, How Kiat LIEW
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Patent number: 11791297Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: GrantFiled: February 4, 2022Date of Patent: October 17, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw Wang, Ch Chew, Eiji Kurose, How Kiat Liew
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Publication number: 20220157756Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: ApplicationFiled: February 4, 2022Publication date: May 19, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw WANG, CH CHEW, Eiji KUROSE, How Kiat LIEW
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Patent number: 11244918Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: GrantFiled: August 17, 2017Date of Patent: February 8, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw Wang, CH Chew, Eiji Kurose, How Kiat Liew
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Publication number: 20210043550Abstract: Implementations of semiconductor packages may include: a lead frame having at least one corner lead, the at least one corner lead positioned where two edges of the package meet, and the at least one lead having a half etch on a first portion of the lead and a half etch on a second portion of the lead. The first portion may extend internally into the package to create a mechanical mold compound lock between a mold compound of the package and the lead. The second portion may be located on at least one of the two edges of the package.Type: ApplicationFiled: October 22, 2020Publication date: February 11, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Soon Wei WANG, How Kiat LIEW, Jose Felixminia PALAGUD, JR.
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Publication number: 20200357697Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: ApplicationFiled: July 30, 2020Publication date: November 12, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh KRISHNAN, Sw Wei WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN
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Patent number: 10825754Abstract: Implementations of semiconductor packages may include: a lead frame having at least one corner lead, the at least one corner lead positioned where two edges of the package meet, and the at least one lead having a half etch on a first portion of the lead and a half etch on a second portion of the lead. The first portion may extend internally into the package to create a mechanical mold compound lock between a mold compound of the package and the lead. The second portion may be located on at least one of the two edges of the package.Type: GrantFiled: August 5, 2016Date of Patent: November 3, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Soon Wei Wang, How Kiat Liew, Jose Felixminia Palagud, Jr.
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Patent number: 10763173Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: GrantFiled: April 26, 2019Date of Patent: September 1, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh Krishnan, Sw Wei Wang, Ch Chew, How Kiat Liew, Fui Fui Tan
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Publication number: 20200035586Abstract: In a general aspect, a chip-on-lead semiconductor device package can include a leadframe having a plurality of signal leads. The plurality of signal leads can include at least two signal leads each having a first face with a first surface area and, opposite the first face, a second face with a second surface area, the second faces of the at least two signal leads being exposed on a surface of the chip-on-lead device package. The plurality of signal lead can also include at least one signal lead having a first face with a third surface area and, opposite the first face of the at least one signal lead, a second face with the second surface area, the second face of the at least one signal lead being exposed on the surface of the chip-on-lead semiconductor device package.Type: ApplicationFiled: July 25, 2018Publication date: January 30, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jin Yoong LIONG, Soon Wei WANG, How Kiat LIEW
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Publication number: 20190252255Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: ApplicationFiled: April 26, 2019Publication date: August 15, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh KRISHNAN, Sw Wei WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN
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Patent number: 10319639Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: GrantFiled: August 17, 2017Date of Patent: June 11, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh Krishnan, Sw Wang, CH Chew, How Kiat Liew, Fui Fui Tan
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Publication number: 20190057947Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Sw WANG, CH CHEW, Eiji KUROSE, How Kiat LIEW
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Publication number: 20190057900Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Shutesh KRISHNAN, Sw WANG, CH CHEW, How Kiat LIEW, Fui Fui TAN
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Publication number: 20180040539Abstract: Implementations of semiconductor packages may include: a lead frame having at least one corner lead, the at least one corner lead positioned where two edges of the package meet, and the at least one lead having a half etch on a first portion of the lead and a half etch on a second portion of the lead. The first portion may extend internally into the package to create a mechanical mold compound lock between a mold compound of the package and the lead. The second portion may be located on at least one of the two edges of the package.Type: ApplicationFiled: August 5, 2016Publication date: February 8, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Soon Wei WANG, How Kiat LIEW, Jose Felixminia PALAGUD, JR.
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Patent number: 9748163Abstract: A chip package, in some embodiments, comprises: a die flag; one or more die supports; and a die mounted on the die flag and on said one or more die supports, at least one surface of said die having an area larger than an area of at least one surface of the die flag.Type: GrantFiled: August 8, 2016Date of Patent: August 29, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Soon Wei Wang, How Kiat Liew, Chee Hiong Chew, Francis J. Carney
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Publication number: 20170162742Abstract: A packaged semiconductor device includes a substrate, a die, at least one electrical connector, a first mold compound formed of translucent material, and a second mold compound. A first face of the die is electrically and mechanically coupled to the substrate. The at least one electrical connector electrically couples at least one electrical contact on a second face of the die with at least one conductive path of the substrate. The first mold compound formed of a translucent material at least partially encapsulates the die and the at least one electrical connector. The second mold compound at least partially encapsulates the first mold compound and forms a window through which the first mold compound is exposed. In implementations the second mold compound is opaque and the first mold compound is transparent. In implementations the substrate includes a lead frame having a die flag and a plurality of lead frame fingers.Type: ApplicationFiled: February 22, 2017Publication date: June 8, 2017Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, How Kiat LIEW, Bih Wen FON
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Publication number: 20160111581Abstract: A packaged semiconductor device includes a substrate, a die, at least one electrical connector, a first mold compound formed of translucent material, and a second mold compound. A first face of the die is electrically and mechanically coupled to the substrate. The at least one electrical connector electrically couples at least one electrical contact on a second face of the die with at least one conductive path of the substrate. The first mold compound formed of a translucent material at least partially encapsulates the die and the at least one electrical connector. The second mold compound at least partially encapsulates the first mold compound and forms a window through which the first mold compound is exposed. In implementations the second mold compound is opaque and the first mold compound is transparent. In implementations the substrate includes a lead frame having a die flag and a plurality of lead frame fingers.Type: ApplicationFiled: October 16, 2014Publication date: April 21, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, How Kiat Liew, Bih Wen Fon
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Patent number: 9281258Abstract: A chip scale package (CSP) includes a die and a first lead mechanically and electrically coupled to a first surface of the die at a first surface of the first lead. The first surface of the first lead forms a first plane. A second lead is mechanically coupled to a second surface of the die at a first surface of the second lead. The first surface of the second lead forms a second plane. A mold compound at least partially encapsulates the die, forming a CSP. The first plane and the second plane are oriented substantially perpendicularly to a third plane formed by a motherboard surface when the CSP is coupled to the motherboard surface. The CSP includes no wirebonds and the first lead and second lead are on opposing surfaces of the CSP. The third plane of the motherboard may be a largest planar surface of the motherboard.Type: GrantFiled: October 30, 2014Date of Patent: March 8, 2016Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Bih Wen Fon, Soon Wei Wang, How Kiat Liew