Abstract: Methods and systems for a digitally controlled oscillator may comprise, for example, an all-digital all digital phase locked loop (ADPLL) for generating an output clock signal from a reference clock signal, the ADPLL comprising a thermometer pulse coder comprising a plurality of frequency control word signal lines. the thermometer pulse coder may be configured to generate a frequency control word from a binary encoded frequency control word, where the frequency control word may comprise hermometer coded signals and a pulse modulated dither signal, and may select a frequency control word signal line over which to transmit the pulse modulated dither signal and may transmit the thermometer coded signals over another of frequency control word signal lines. A digitally controlled oscillator may be configured to receive a frequency control word and generate an output clock signal at a frequency determined using at least the frequency control word.

Abstract: Methods and systems for a digitally controlled oscillator may comprise, for example, an all-digital all digital phase locked loop (ADPLL) for generating an output clock signal from a reference clock signal, the ADPLL comprising a thermometer pulse coder comprising a plurality of frequency control word signal lines. the thermometer pulse coder may be configured to generate a frequency control word from a binary encoded frequency control word, where the frequency control word may comprise hermometer coded signals and a pulse modulated dither signal, and may select a frequency control word signal line over which to transmit the pulse modulated dither signal and may transmit the thermometer coded signals over another of frequency control word signal lines. A digitally controlled oscillator may be configured to receive a frequency control word and generate an output clock signal at a frequency determined using at least the frequency control word.

Abstract: A method and system for a multi-rate Media Access Control layer (MAC) to Physical layer (PHY) interface is provided. The method to provide a multi-rate Media Access Control layer (MAC) interface comprises receiving a first set of signals, sampling the first set of signals to determine a type of interface to be used to transmit or receive the first set of signals or a subset of the first set of signals, generating a select signal indicating type of interface to be used based on the sampling step and transmitting the first set of signals or a subset of the first set of signals using the interface indicated by the select signal.

Abstract: A multi-port SERDES transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port SERDES transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Abstract: Systems and methods for generating a thermometer sigma delta encoded frequency control word for controlling a digitally controlled oscillator in accordance with embodiments of the invention are disclosed. In one embodiment, an all digital phase locked loop for generating an output clock signal includes a thermometer pulse coder configured to generate a frequency control word (FCW) that includes thermometer coded signals and a pulse modulated dither signal, and transmit the pulse modulated dither signal over a selected FCW signal line and transmit the thermometer coded signals over other FCW signal lines, and a digitally controlled oscillator to receive a FCW comprising a combined thermometer and pulse modulated signal and generate an output clock signal.

Abstract: Methods and systems adaptively equalizing an analog information signal, the method including sampling the analog information signal to provide analog samples including post-transition samples and steady-state samples, and equalizing the analog samples to produce equalized analog samples. The equalizing includes determining a difference between an average post-transition amplitude associated with at least one of the post-transition samples and an average steady-state amplitude associated with at least one of the steady-state samples, and adjusting an equalization coefficient to adjust the difference between the average post-transition amplitude and the average steady-state amplitude.

Abstract: A method and system for a multi-rate Media Access Control layer (MAC) to Physical layer (PHY) interface is provided. The method to provide a multi-rate Media Access Control layer (MAC) interface comprises receiving a first set of signals, sampling the first set of signals to determine a type of interface to be used to transmit or receive the first set of signals or a subset of the first set of signals, generating a select signal indicating type of interface to be used based on the sampling step and transmitting the first set of signals or a subset of the first set of signals using the interface indicated by the select signal.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A method and system for a multi-rate Media Access Control layer (MAC) to Physical layer (PHY) interface is provided. The method to provide a multi-rate Media Access Control layer (MAC) interface comprises receiving a first set of signals, sampling the first set of signals to determine a type of interface to be used to transmit or receive the first set of signals or a subset of the first set of signals, generating a select signal indicating type of interface to be used based on the sampling step and transmitting the first set of signals or a subset of the first set of signals using the interface indicated by the select signal.

Abstract: Systems and methods for generating a thermometer sigma delta encoded frequency control word for controlling a digitally controlled oscillator in accordance with embodiments of the invention are disclosed. In one embodiment, an all digital phase locked loop for generating an output clock signal includes a thermometer pulse coder configured to generate a frequency control word (FCW) that includes thermometer coded signals and a pulse modulated dither signal, and transmit the pulse modulated dither signal over a selected FCW signal line and transmit the thermometer coded signals over other FCW signal lines, and a digitally controlled oscillator to receive a FCW comprising a combined thermometer and pulse modulated signal and generate an output clock signal.

Abstract: Methods and systems adaptively equalizing an analog information signal, the method including sampling the analog information signal to provide analog samples including post-transition samples and steady-state samples, and equalizing the analog samples to produce equalized analog samples. The equalizing includes determining a difference between an average post-transition amplitude associated with at least one of the post-transition samples and an average steady-state amplitude associated with at least one of the steady-state samples, and adjusting an equalization coefficient to adjust the difference between the average post-transition amplitude and the average steady-state amplitude.

Abstract: Systems and methods for generating a thermometer sigma delta encoded frequency control word for controlling a digitally controlled oscillator in accordance with embodiments of the invention are disclosed. In one embodiment, an all digital phase locked loop for generating an output clock signal includes a thermometer pulse coder configured to generate a frequency control word (FCW) that includes thermometer coded signals and a pulse modulated dither signal, and transmit the pulse modulated dither signal over a selected FCW signal line and transmit the thermometer coded signals over other FCW signal lines, and a digitally controlled oscillator to receive a FCW comprising a combined thermometer and pulse modulated signal and generate an output clock signal.

Abstract: Methods and systems for adaptively equalizing an analog information signal for a signal path, including sampling the analog information signal, thereby generating analog samples, and performing an equalizing process on the analog samples, wherein the equalizing includes processing an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples to produce equalized analog samples.

Abstract: A communications network includes a management device and a remote device. The remote device includes a physical layer device (PHY) coupled to a link partner. An independent station manager of the remote device provides the bi-directional exchange of management information between the PHY and a serial-to-parallel (S/P) interface connecting the remote device and the management device. A station manager of the management device provides the bi-directional exchange of management information between the S/P interface and a Media Access Controller (MAC) of the management device. The independent station manager and the station manager transmit initiation messages, formatted according to a message template of an Auto-Negotiation (AN) routine of the S/P interface reserved for customization, to reserve an embedded management channel for the transfer of management information.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled to a master timing generator and a transmission module. The phase interpolator is also coupled to a receiver interpolator control module and/or an external interpolator control module. When the system is operating in repeat mode, the transmitter phase interpolator receives a control signal from a receiver interpolator control module. The transmitter phase interpolator uses the signal to synchronize the transmission clock to the sampling clock. When the system is operating in test mode, a user defines a transmission data profile in an external interpolator control module. The external interpolator control module generates a control signal based on the profile. The transmitter phase interpolator uses the signal to generate a transmission clock that is used by the transmission module to generate a data stream having the desired profile.

Abstract: Methods and systems for adaptively equalizing an analog information signal for a signal path, including sampling the analog information signal, thereby generating analog samples, and performing an equalizing process on the analog samples, wherein the equalizing includes processing an average of post-transition sample amplitudes and an average of steady state sample amplitudes of the analog samples to produce equalized analog samples.

Abstract: A multi-port SERDES transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port SERDES transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Abstract: Methods and systems for minimizing distortions in an analog data signal include equalizing the analog data signal at a receive end. In an embodiment, the invention adapts equalization parameters to a signal path associated with the analog data signal. Adaptive control logic is implemented with analog and/or digital components. In an embodiment, the invention equalizes a discrete-time analog representation of an analog data signal. In an embodiment, the invention digitally controls equalization parameters. In an embodiment, a resultant equalized analog data signal is digitized. In an example implementation, an analog data signal is sampled, a quality of the samples is measured, and one or more equalization parameters are adjusted with digital controls as needed to minimize distortion of the samples. The equalized samples are then digitized. The present invention is suitable for lower rate analog data signals and multi-gigabit data rate analog signals.

Abstract: A method for performing Iddq testing including receiving an Iddq message and executing the Iddq message to measure current leakage.