Patents by Inventor Howard Calkin

Howard Calkin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9645857
    Abstract: In accordance with at least some embodiments, a system includes a plurality of partitions, each partition having its own operating system (OS) and workload. The system also includes a plurality of resources assignable to the plurality of partitions. The system also includes management logic coupled to the plurality of partitions and the plurality of resources. The management logic is configured to set priority rules for each of the plurality of partitions based on user input. The management logic performs automated resource fault management for the resources assigned to the plurality of partitions based on the priority rules.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: May 9, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Andrew C. Walton, Jeffrey A. Barlow, Howard Calkin
  • Patent number: 8667324
    Abstract: In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: March 4, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 8661289
    Abstract: In one embodiment, a CPU cache management system is provided. The CPU management system includes, for example, a CPU chip and cache management logic. The CPU chip include cache elements that are initially in use and spare cache elements that not initially in use. The cache management logic determines whether currently-used cache elements are faulty. If a cache element is determined to be faulty, the cache management logic schedules a reboot of the computer and swaps in a spare cache element for the faulty currently-used cache element during the reboot.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: February 25, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 8230261
    Abstract: A system and method for managing faults in a computer-based system are disclosed herein. For example, a system includes fault management logic, and a plurality of field replaceable units (“FRUs”). In response to a detected fault in the system, the fault management logic is configured to identify each FRU of a sub-plurality of the FRUs as a possible root cause of the fault. The fault management logic is further configured to store information, including an acquittal policy, that individually specifies for each identified FRU whether to dismiss the identified FRU from the sub-plurality based on detection of an event corresponding to the identified FRU.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: July 24, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Howard Calkin
  • Patent number: 8161324
    Abstract: A system and method for recording fault information in an electronic system are disclosed herein. A system includes fault analysis logic and a plurality of field replaceable units (“FRUs”). The fault analysis is configured to analyze system error information, and identify at least one of the FRUs in the system to be a possible cause of a detected fault based on the analysis. Each FRU includes writeable non-volatile storage including storage locations reserved to store information including a result of the analysis. The result of the analysis indicates a reason that the FRU storing the information was determined, by the fault analysis logic, to be a possible cause of the fault.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: April 17, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Howard Calkin, Andrew C. Walton
  • Patent number: 8151147
    Abstract: In accordance with at least some embodiments, a system comprises a plurality of partitions, each partition having its own error handler. The system further comprises a plurality of resources assignable to the plurality of partitions. The system further comprises management logic coupled to the plurality of partitions and the plurality of resources. The management logic comprises an error management tool that synchronizes operation of the error handlers in response to an error.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: April 3, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Anurupa Rajkumari, Andrew C. Walton, Howard Calkin
  • Patent number: 8122290
    Abstract: A system for error log consolidation is disclosed herein. A server computer includes a plurality of system processors and error log consolidation logic. The system processors are configurable to form isolated execution partitions. The error log consolidation logic is configured to, based on detection of a fault in the server, retrieve error logs from the system processors, and to consolidate the retrieved logs with server computer information not available to the system processors to generate a consolidated error log. The consolidated error log includes a comprehensive set of server information relevant to identifying a cause of the detected fault.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: February 21, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Andrew C. Walton, Howard Calkin, Anurupa Rajkumari
  • Patent number: 8108724
    Abstract: A system and method for fault management in a computer-based system are disclosed herein. A system includes a plurality of field replaceable units (“FRUs”) and fault management logic. The fault management logic is configured to collect error information from a plurality of components of the system. The logic stores, for each component identified as a possible cause of a detected fault, a record assigning one of two different component failure probability indications. The logic identifies a single of the plurality of FRUs that has failed based on the stored probability indications.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: January 31, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeffrey A. Barlow, Howard Calkin, Andrew C. Walton, Anurupa Rajkumari
  • Publication number: 20110154128
    Abstract: In accordance with at least some embodiments, a system comprises a plurality of partitions, each partition having its own error handler. The system further comprises a plurality of resources assignable to the plurality of partitions. The system further comprises management logic coupled to the plurality of partitions and the plurality of resources. The management logic comprises an error management tool that synchronizes operation of the error handlers in response to an error.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Inventors: Anurupa Rajkumari, Andrew C. Walton, Howard Calkin
  • Publication number: 20110154114
    Abstract: A system and method for managing faults in a computer-based system are disclosed herein. For example, a system includes fault management logic, and a plurality of field replaceable units (“FRUs”). In response to a detected fault in the system, the fault management logic is configured to identify each FRU of a sub-plurality of the FRUs as a possible root cause of the fault. The fault management logic is further configured to store information, including an acquittal policy, that individually specifies for each identified FRU whether to dismiss the identified FRU from the sub-plurality based on detection of an event corresponding to the identified FRU.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Inventor: Howard CALKIN
  • Publication number: 20110154349
    Abstract: In accordance with at least some embodiments, a system includes a plurality of partitions, each partition having its own operating system (OS) and workload. The system also includes a plurality of resources assignable to the plurality of partitions. The system also includes management logic coupled to the plurality of partitions and the plurality of resources. The management logic is configured to set priority rules for each of the plurality of partitions based on user input. The management logic performs automated resource fault management for the resources assigned to the plurality of partitions based on the priority rules.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Inventors: Andrew C. Walton, Jeffrey A. Barlow, Howard Calkin
  • Publication number: 20110154097
    Abstract: A system and method for fault management in a computer-based system are disclosed herein. A system includes a plurality of field replaceable units (“FRUs”) and fault management logic. The fault management logic is configured to collect error information from a plurality of components of the system. The logic stores, for each component identified as a possible cause of a detected fault, a record assigning one of two different component failure probability indications. The logic identifies a single of the plurality of FRUs that has failed based on the stored probability indications.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Inventors: Jeffrey A. BARLOW, Howard Calkin, Andrew C. Walton, Anurupa Rajkumari
  • Publication number: 20110154115
    Abstract: A system and method for recording fault information in an electronic system are disclosed herein. A system includes fault analysis logic and a plurality of field replaceable units (“FRUs”). The fault analysis is configured to analyze system error information, and identify at least one of the FRUs in the system to be a possible cause of a detected fault based on the analysis. Each FRU includes writeable non-volatile storage including storage locations reserved to store information including a result of the analysis. The result of the analysis indicates a reason that the FRU storing the information was determined, by the fault analysis logic, to be a possible cause of the fault.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Inventors: Howard CALKIN, Andrew C. WALTON
  • Publication number: 20110154091
    Abstract: A system for error log consolidation is disclosed herein. A server computer includes a plurality of system processors and error log consolidation logic. The system processors are configurable to form isolated execution partitions. The error log consolidation logic is configured to, based on detection of a fault in the server, retrieve error logs from the system processors, and to consolidate the retrieved logs with server computer information not available to the system processors to generate a consolidated error log. The consolidated error log includes a comprehensive set of server information relevant to identifying a cause of the detected fault.
    Type: Application
    Filed: December 17, 2009
    Publication date: June 23, 2011
    Inventors: Andrew C. WALTON, Howard CALKIN, Anurupa RAJKUMARI
  • Patent number: 7917804
    Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: March 29, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 7694175
    Abstract: Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example, initializing and executing an operating system, de-allocating the processor from the available pool or system resources and performing a health-check on the processor while the operating system is executing.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: April 6, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Ray Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 7694174
    Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: April 6, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 7673171
    Abstract: Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: March 2, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 7607038
    Abstract: In one embodiment, a method for repairing a faulty cache element is provided. Once a monitored cache element is determined to be faulty, the system stores the repair information, and cache configuration in an EEPROM or non-volatile memory on the CPU module. Then the computer is rebooted. During the reboot, the faulty cache element is repaired by being swapped out for a spare cache element based on the information stored in the EEPROM or the non-volatile memory.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: October 20, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmak
  • Patent number: 7607040
    Abstract: Systems and methods for conducting processor health-checks are provided. In one embodiment, a method for evaluating the status of a processor is provided. The method includes, for example, initializing and executing an operating system, de-allocating the processor from the available pool or system resources and performing a health-check on the processor while the operating system is executing.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: October 20, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jeff Barlow, Jeff Brauch, Howard Calkin, Raymond Gratias, Stephen Hack, Lacey Joyal, Guy Kuntz, Ken Pomaranski, Michael Sedmark