Patents by Inventor Howard CHI

Howard CHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10541647
    Abstract: Transconductance (gm)-cell based circuitry is well suited for low power, low voltage complementary metal oxide silicon (CMOS) design in deep sub micro technology. This circuitry includes a gm cell as the basic building block. As such, it is desirable to have the transconductance of the gm cell to be constant against temperature and process corners. The present disclosure describes various gm-cell based circuitry having a controllable transconductance. Preferably, the controllable transconductance can be selectively controlled to be equal to the inverse of the value of an on-chip resistor. For example, the gm-cell based circuitry can sense the transconductance of an internal replica unit and can use negative feedback circuitry to cause this transconductance to be approximately equal a value of an on-chip resistor. However, in some situations, a value of this on-chip resistor is not accurately controlled.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: January 21, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Howard Chi, Seema B. Anand
  • Patent number: 10250200
    Abstract: The present disclosure is directed to a dual output path LNA that can be used to break the tradeoff between the output impedance and linearity of an LNA without the problems of a programmable output impedance LNA. In an embodiment, the dual output path architecture includes an LNA driving a low level of impedance in a low voltage gain path, thus achieving high linearity in the presence of large blockers, and driving a high level of impedance in a high voltage gain path to increase the LNA's voltage gain and minimize performance degradation due to a noisier, low power receiver front-end chain following the LNA. The present disclosure is further directed to a local oscillator (LO) offset circuit with low power and reduced spur generation.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: April 2, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Valentina Della Torre, Seema B. Anand, Howard Chi, Matteo Conta
  • Patent number: 10243518
    Abstract: The present disclosure is directed to a dual output path LNA that can be used to break the tradeoff between the output impedance and linearity of an LNA without the problems of a programmable output impedance LNA. In an embodiment, the dual output path architecture includes an LNA driving a low level of impedance in a low voltage gain path, thus achieving high linearity in the presence of large blockers, and driving a high level of impedance in a high voltage gain path to increase the LNA's voltage gain and minimize performance degradation due to a noisier, low power receiver front-end chain following the LNA. The present disclosure is further directed to a local oscillator (LO) offset circuit with low power and reduced spur generation.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: March 26, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Valentina Della Torre, Seema B. Anand, Howard Chi, Matteo Conta
  • Publication number: 20180076837
    Abstract: The present disclosure is directed to a dual output path LNA that can be used to break the tradeoff between the output impedance and linearity of an LNA without the problems of a programmable output impedance LNA. In an embodiment, the dual output path architecture includes an LNA driving a low level of impedance in a low voltage gain path, thus achieving high linearity in the presence of large blockers, and driving a high level of impedance in a high voltage gain path to increase the LNA's voltage gain and minimize performance degradation due to a noisier, low power receiver front-end chain following the LNA. The present disclosure is further directed to a local oscillator (LO) offset circuit with low power and reduced spur generation.
    Type: Application
    Filed: September 6, 2017
    Publication date: March 15, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Valentina Della TORRE, Seema B. ANAND, Howard CHI, Matteo CONTA
  • Publication number: 20180076775
    Abstract: The present disclosure is directed to a dual output path LNA that can be used to break the tradeoff between the output impedance and linearity of an LNA without the problems of a programmable output impedance LNA. In an embodiment, the dual output path architecture includes an LNA driving a low level of impedance in a low voltage gain path, thus achieving high linearity in the presence of large blockers, and driving a high level of impedance in a high voltage gain path to increase the LNA's voltage gain and minimize performance degradation due to a noisier, low power receiver front-end chain following the LNA. The present disclosure is further directed to a local oscillator (LO) offset circuit with low power and reduced spur generation.
    Type: Application
    Filed: September 6, 2017
    Publication date: March 15, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Valentina Della TORRE, Seema B. ANAND, Howard CHI, Matteo CONTA
  • Publication number: 20180076767
    Abstract: Transconductance (gm)-cell based circuitry is well suited for low power, low voltage complementary metal oxide silicon (CMOS) design in deep sub micro technology. This circuitry includes a gm cell as the basic building block. As such, it is desirable to have the transconductance of the gm cell to be constant against temperature and process corners. The present disclosure describes various gm-cell based circuitry having a controllable transconductance. Preferably, the controllable transconductance can be selectively controlled to be equal to the inverse of the value of an on-chip resistor. For example, the gm-cell based circuitry can sense the transconductance of an internal replica unit and can use negative feedback circuitry to cause this transconductance to be approximately equal a value of an on-chip resistor. However, in some situations, a value of this on-chip resistor is not accurately controlled.
    Type: Application
    Filed: September 12, 2017
    Publication date: March 15, 2018
    Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Howard CHI, Seema B. ANAND
  • Publication number: 20120107317
    Abstract: The subject invention provides novel uses of cytoplasmic c-Myc for modulation of innate immune responses. The invention is based, at least in part, on the surprising discovery that cytoplasmic c-Myc, instead of nuclear c-Myc, modulates pro-inflammatory immune responses via its role as a positive feedback regulator. Specifically, the subject invention provides methods for treatment or amelioration of inflammatory diseases and/or immune disorders via inhibition c-Myc expression or its activity. Also provided are methods for the development of therapeutic agents for treating infection, inflammation, immune diseases and autoimmune diseases.
    Type: Application
    Filed: October 26, 2011
    Publication date: May 3, 2012
    Applicant: The University of Hong Kong
    Inventors: ALLAN SIK YIN LAU, Howard Chi Ho Yim, Chun Bong Li, John Chi Him Pong