Abstract: A method is described for forming three or more spacer widths in transistor regions on a substrate. In one embodiment, different silicon nitride thicknesses are formed above gate electrodes followed by nitride etching to form spacers. Optionally, different gate electrode thicknesses may be fabricated and a conformal oxide layer is deposited which is subsequently etched to form different oxide spacer widths. A third embodiment involves a combination of different gate electrode thickness and different nitride thicknesses. A fourth embodiment involves selectively thinning an oxide layer over certain gate electrodes before etching to form spacers. Therefore, spacer widths can be independently optimized for different transistor regions on a substrate to enable better drive current in transistors with narrow spacers and improved SCE control in neighboring transistors with wider spacers. Better drive current is also obtained in transistors with shorter polysilicon thickness.

Abstract: A method of forming a pocket implant region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an indium pocket implant region, in the area of a P type semiconductor to be used to accommodate an N type source/drain region, an ion implantation procedure is used to place antimony ions in the indium pocket implant region. The presence of antimony ions limits the broadening of the indium pocket implant profile during subsequent anneal procedures, used to activate implanted ions. Formation of an implanted, lightly doped, N type source/drain region, insulator spacers on the sides of a gate structure, and formation of a heavily doped, N type, source/drain region, complete the process sequence used to form the NMOS, transfer gate transistor.

Abstract: A method of forming an implanted pocket region, to reduce short channel effects (SCE), for narrow channel length, NMOS devices, has been developed. After forming an initial indium pocket region, with an initial indium profile, in the area of a P type semiconductor to be used to accommodate an N type source/drain region, a low temperature anneal procedure is used to activate indium ions in the initial indium pocket region, and to create a final indium pocket region, featuring a final indium profile. The final indium profile remains unchanged after experiencing subsequent high temperature procedures, such as a post-heavily doped, source/drain anneal. The narrow channel length NMOS devices, fabricated using the low temperature anneal procedure described in this invention, resulted in a reduced Vt roll-off phenomena, when compared to counterpart, narrow channel length NMOS, formed without the benefit of the low temperature anneal procedure.