Abstract: An input buffer within an integrated circuit capable of receiving an input signal that complies with the electrical characteristic voltage levels of TTL, LVTTL, SSTL, or GTL, buffering the input signal, and converting the input signal to an output signal having voltage levels acceptable to internal circuitry of the integrated circuits is described. The input buffer will have an adjustable threshold trip point at which the input signal will cause the output signal to change between a first logic state and a second logic state. The adjustable threshold trip point will be determined by an adjustment voltage circuit that is immune to variation in semiconductor processing parameters, power supply voltage and operating temperature.

Abstract: A method and apparatus of an output buffer for controlling the ground bounce and power supply noise during output switching is provided. A CMOS output buffer comprises a P-channel output transistor, a N-channel output transistor and a predrive circuit. During output pull-down transition, the predrive circuit generates a first gate voltage on the pull-down N-channel output transistor for a predetermined time, and further generates a second voltage value which is smaller than the first voltage value, then returns to the first voltage value after the elapse of the predetermined time. The predrive circuit makes the pull-down N-channel output transistor stay in the saturation region longer than the uncontrolled scheme, the steep rising gate voltage on the N-channel output transistor can be avoided with a very little speed degradation but instead of better ground bounce improvement.

Abstract: An input buffer within an integrated circuit capable of receiving an input signal that complies with the electrical characteristic voltage levels of TTL, LVTTL, SSTL, or GTL, buffering the input signal, and converting the input signal to an output signal having voltage levels acceptable to internal circuitry of the integrated circuits is described. The input buffer will have an adjustable threshold trip point at which the input signal will cause the output signal to change between a first logic state and a second logic state. The adjustable threshold trip point will be determined by an adjustment voltage circuit that is immune to variation in semiconductor processing parameters, power supply voltage and operating temperature.

Abstract: This invention describes a delay circuit for integrated circuits that has the capability to delay the rising and falling transitions separately and independent of each other. A signal is fed through an RC network to a Schmitt trigger and then through an inverter to the output of the delay circuit. Two MOS transistors are connected as capacitors and in parallel but in opposing directions between the delay circuit output and the input to the Schmitt trigger to form part of the RC network. The biasing of the two transistors is such that the inversion layer capacitance is active in only one transistor for each signal transition. Thus the falling and rising transition of an input signal can be delayed separately. Changing the gate and channel size in one transistor acting as a capacitor changes the delay in one signal transition. Changing the other gate and channel size changes the delay in the other transition.

Abstract: Circuits and a method are described that integrate memory arrays, a redundant memory array, their associated decoders, sense amplifiers, and outputs into one module. This integration is achieved through the use of a column decoder with a fuse, which, when blown, permanently deselects the failing array and selects the redundant array. By OR'ing the redundant column select line of each column decoder, any column decoder can select the redundant array. Higher level array structures are produced by replication of the lower level array structure. The system output is generated by OR'ing together the respective data outputs of each array.

Abstract: The invention is a method of forming a reduced cost DRAM. The process has two embodiments for forming twin wells and two embodiments for forming pillar shaped capacitor electrodes. The twin well embodiments are simple low cost processes. The embodiments for forming the electrode pillars begin by forming a tungsten silicide conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller that the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. This first embodiment for fabricating the multiple pillar capacitor forms pillars of a smaller dimension than the resolution of the photolithography tool.