Abstract: Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the, same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.

Abstract: Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.

Abstract: An RF power device comprising a power transistor fabricated in a first semiconductor chip and a MOSCAP type structure fabricated in a second semiconductor chip. A voltage limiting device is provided for protecting the power transistor from input voltage spikes and is preferably fabricated in the semiconductor chip along with the MOSCAP. Alternatively, the voltage limiting device can be a discrete element fabricated on or adjacent to the capacitor semiconductor chip. By removing the voltage limiting device from the power transistor chip, fabrication and testing of the voltage limiting device is enhanced, and semiconductor area for the power device is increased and aids in flexibility of device fabrication.

Abstract: An inexpensive method of providing uniform and consistent spacing between a semiconductor die and a supporting substrate includes providing relatively rigid spacers such as a plurality of lengths of wires or a plurality of bumps on the mounting surface for the chip. The spacers allow a uniform desired spacing of the die from the supporting substrate when attached by an epoxy.

Abstract: An RF power device comprising a power transistor fabricated in a first semiconductor chip and a MOSCAP type structure fabricated in a second semiconductor chip. A voltage limiting device is provided for protecting the power transistor from input voltage spikes and is preferably fabricated in the semiconductor chip along with the MOSCAP. Alternatively, the voltage limiting device can be a discrete element fabricated on or adjacent to the capacitor semiconductor chip. By removing the voltage limiting device from the power transistor chip, fabrication and testing of the voltage limiting device is enhanced, and semiconductor area for the power device is increased and aids in flexibility of device fabrication.

Abstract: An inexpensive method of providing uniform and consistent spacing between a semiconductor die and a supporting substrate includes providing relatively rigid spacers such as a plurality of lengths of wires or a plurality of bumps on the mounting surface for the chip. The spacers allow a uniform desired spacing of the die from the supporting substrate when attached by an epoxy.

Abstract: The power delivered by an RF power transistor having cascaded cells or unit elements is improved by reducing the phase imbalance between elements and thereby reducing transverse effects between cells. Phase imbalance is reduced by varying the number of transistor elements connected to interconnect areas, connecting wire bonds to an input transmission line concentrated near an outer edge in the transmission line to take advantage of surface skin effects on current, and varying the surface area of the interconnect areas to adjust input impedance and output impedance of each cell.

Abstract: A power semiconductor device package in which a semiconductor chip is mounted on a ceramic platform and sealed thereon by a lid. The platform has opposing end portions which receive fasteners for directly fastening the platform and semiconductor device to a heat sink without the requirement of a separate mounting clamp. In one embodiment, metal films are provided on a surface of the platform adjacent to recesses for receiving the fasteners. The metal films function to distribute the stress of the fasteners over the surface of the end portions thereby minimizing the possibility of fracture of the ceramic platform.

Abstract: A linear MOSFET device includes a shield plate positioned between a drain and an overlying gate. A voltage bias is applied to the shield plate to maintain linear operation of the device for RF power amplification. An AC ground is preferably connected to the shield plate. The voltage bias can be varied for matching of parallel connected devices, for responding to peak input signals, and for temperature compensation.

Abstract: A ceramic package and mounting structure which requires less surface area on a heat sink and improves heat transfer to the heat sink. Each ceramic package has a top side and a bottom side with the bottom side being flat and smooth. The bottom side can be a polished ceramic, or metal layer which is plated or brazed to the bottom side. The mounting structure includes a clamp and a spring in pressure engagement with the top side of the package for maintaining the package in pressure engagement with the heat sink.

Abstract: Operating characteristics of an electronics device in which alternating currents flow are improved by reducing positive electromagnetic coupling between currents. This is accomplished by altering the direction of a current flow to obtain negative coupling through current flow in the same direction, or by minimizing electromagnetic coupling through perpendicular current flow, or by increasing the spacing between two electromagnetically coupled currents. In a bipolar transistor structure a feed structure for emitter and base current includes wire bonding pads aligned so that emitter current and base current flow to wire bonding pads perpendicular to the direction of collector current flow and with adjacent emitter currents and base currents flowing in the same direction. Each feed structure includes a plurality of interdigitated fingers for contacting emitter and base regions, all emitter and base currents in said interdigitated fingers of all feed structures flowing in the same direction as the collector.

Abstract: An RF power transistor is mounted on a ceramic substrate with a plurality of input leads extending from one edge of the substrate, a plurality of output leads extending from an opposite edge of the substrate, a plurality of input ground leads with ground leads positioned between adjacent input leads, and a plurality of output ground leads with ground lead positioned between adjacent output leads. All ground leads are ohmically connected with the current paths between adjacent ground leads reduced in length.

Abstract: The feeds to the emitter, base, and collector of an RF power transistor (source, drain, gate feeds of an RF FET) are configured so that negative mutual coupling therebetween is enhanced and positive mutual coupling therebetween is reduced. The emitter and base feeds include elongated portions which are generally parallel to each other with bonding pads provided on the elongated portions so that emitter and base currents flow in the same direction in the elongated portions and in the same direction as collector currents below. Interdigitated contact fingers extend from the elongated portions and contact the emitter region and the base region, respectively. When positive coupling of collector current and emitter current to the controlling base current is reduced or eliminated, the major thermal imbalance problem of operating RF transistors is also reduced or eliminated. Performance, linearity, efficiency, gain, and ruggedness are all enhanced in devices designed to utilize this invention.

Abstract: An RF power device including a DMOS field effect transistor has increased efficiency and reduced distortion. A capacitor is connected between the gate and source input of the transistor which swamps non-linear variations of the parasitic capacitance (C.sub.GD) between the gate and drain, thereby offsetting the Miller effect of the feedback provided by the MOS transistor parasitic capacitance. The capacitor, the Ciss of the MOS transistor, and the inductance of input leads provide a device input resonant frequency between the input signal fundamental frequency and the first harmonic.

Abstract: Thermal balance in an array of RF transistor cells in which all transistors are connected in parallel is obtained by interconnecting the transistors to array contacts by means of discrete wire leads. The array is electrically tested and a temperature distribution in the array is obtained. Thereafter, the wire leads are varied in length and height above the plane of the array to improve temperature distribution during test. The steps are repeated as necessary to obtain a desired temperature balance in the array.

Abstract: An improved dual metallization process in which self-aligned tungsten contacts are formed to closely-spaced emitter or source sites in RF power silicon devices. Low-resistivity ohmic contacts are made by selectively depositing tungsten on the exposed silicon surfaces as a first metal layer without a photomasking process and after a dielectric layer deposition and via opening process. The metallization process is completed by depositing a second metal or polysilicon layer on the dielectric layer and through vias to selected tungsten contacts. The tungsten combines with doped silicon in the emitter or source regions to form the low-resistivity ohmic contacts without the requirement of a platinum or palladium deposition and siliciding step as in prior art. The tungsten is preferably chemical-vapor-deposited in a two-temperature step when a first few hundred Angstroms of tungsten are grown at a low temperature on the order of 250.degree. C.-350.degree. C.

Abstract: Provided is a process for forming a contact for a compound semiconductor device without electrically shorting the device. In one embodiment, a highly doped compound semiconductor material is electrically connected to a compound semiconductor material of the same conductivity type through an opening in a compound semiconductor material of the opposite conductivity type. Another embodiment discloses a transistor including multiple compound semiconductor layers where a highly doped compound semiconductor material is electrically connected to a compound semiconductor layer of the same conductivity type through an opening in a compound semiconductor layer of the opposite conductivity type. Embodiments further include metal contacts electrically connected to the highly doped compound semiconductor material. A substantially planar semiconductor device is disclosed. In embodiments, the compound semiconductor material may be silicon carbide.