Abstract: A single finite impulse response filter designed to operate on a single signal is used in conjunction with an input multiplexer that interleaves samples from multiple signals and an output decimator. The output of the decimator contains interleaved samples of the multiple signals with independent filtering applied to each.

Abstract: A single finite impulse response filter designed to operate on a single signal is used in conjunction with an input multiplexer that interleaves samples from multiple signals and an output decimator. The output of the decimator contains interleaved samples of the multiple signals with independent filtering applied to each.

Abstract: Data values representing the (I2+Q2) values are converted to floating-point representations and a histogram of the floating-point numbers is generated. The count for each histogram bin in the histogram is stored in a memory. Each floating-point number acts as an address for a corresponding histogram bin in the memory. The accumulated counts in the histogram bins are then grouped into a desired number of CCDF bins, and the CCDF curve is derived from the histogram data. Grouping the histogram bins into the CCDF bins may include combining one or more histogram bins into a single CCDF bin. Linear interpolation is used to divide a count value in a histogram bin between two CCDF bins when the histogram bin does not align with a single CCDF bin.

Abstract: One embodiment of the invention includes a system comprising an analog baseband signal input, a conversion circuit with N Analog to Digital Converters (ADCs) operable to receive the analog baseband signal, and a Finite Impulse Response (FIR) filter operable to receive outputs of the N ADCs and to produce a digital representation of the analog baseband signal corrected for a mismatch in the N ADCs.

Abstract: Nondeterministic rounding of fixed point values in a digital signal processor. A pseud-random value is generated and a preselcted number of pseudo-random bits are added to the result to be rounded prior to truncation being applied. Pseudo-random numbers may be generated by means including two maximal-length pseudo-random sequence generators.

Abstract: Correction of differences between two analog to digital converters (ADCs) in broadband intermediate frequency conversion. By stimulating a two-ADC system with a known input, the impulse response of the system is derived, and from that impulse response a finite impulse response filter is derived which corrects for mismatches between the ADCs.

Abstract: Correction of differences between two analog to digital converters (ADCs) in broadband intermediate frequency conversion. By stimulating a two-ADC system with a known input, the impulse response of the system is derived, and from that impulse response a finite impulse response filter is derived which corrects for mismatches between the ADCs.

Abstract: In generating, transmitting, and receiving data signals, various forms of complex modulation formats are often used and the signals are most often processed as two component (I, Q) signals. Such modulated signals are subject to a variety of impairments due to imperfections in the various elements in the transmission chain. For the large class of essentially linear impairment processes, the impairments may be removed with compensating filters, one filter being assigned to each impairment. In this invention, the generalized filter, a new class of two-channel filters for compensating impairments, is disclosed. Compared with previous two-channel filters, which are characterized by two impulse responses, the generalized filter is characterized by four such impulse responses. This filter can simultaneously compensate a plurality of diverse impairments.

Abstract: A versatile signal generator for generating digitally modulated test signals computed in real-time is provided. Each of the blocks ol the versatile signal generator, including the MUX, coder, map, filter, re-sampler, and modulator, are implemented in a sufficiently flexible manner so as to allow ready configuration to produce any of a variety of digitally modulated signals as well as high quality analog modulated signals. Each of the blocks may be implemented using ASICs and RAM that allow to obtain high symbol rates while being capable of being reconfigured for different test signals as needed. The versatile signal generator has a real time input for receiving input data to modulate the test signal in real time.

Abstract: A phase detector for symbol clock recovery in a digital communications system determines the phase error of a local symbol clock from the symbol rate of a transmitted signal by sampling the transmitted signal to obtain a first sample at a fraction of a symbol period after the symbol clock and to obtain a second sample at an equal fraction of a symbol period before the symbol clock, and determining a phase error equal to the difference between a function of the magnitude of the first sample and a function of the magnitude of the second sample. The function is preferably the square of the magnitude or the logarithm of the magnitude of the samples.

Abstract: An ECG recorder and playback unit which includes software-implemented digital signal processing filters which compensate for phase and magnitude distortion occurring when an ECG signal is recorded on a Holter recorder and played back. This permits "tuning" a recorder and playback unit which may be unrelated, as when made by different manufacturers. An impulse or step signal is recorded and played back to provide a system frequency response measurement. Coefficients for a digital correction filter are derived from the discrete Fourier transform of the impulse or step response and a desired system response. When recorded ECG data is played back, it is filtered on a substantially real-time basis with the digital correction filter to compensate for phase and magnitude distortion. Prior to recording, the high frequencies of the ECG signal are boosted to compensate for high frequency losses inherent in the recording and playing back of ECG signals.

Abstract: A sensor is disclosed which exchanges with associated data acquisition equipment a digital attribute signal, distinct from its transducer output signal, on the occurrence of a predetermined event. The invention is particularly illustrated with reference to an accelerometer which transmits sensor identification data to associated data acquisition equipment when power is first applied by using the same two signal lines as are used to provide power to the sensor and to convey the sensor output signal to the equipment. After the identification data is transmitted, the apparatus operates as a buffer amplifier to modulate the transducer output signal onto the same two signal lines.

Abstract: Errors in a sampled data process are discerned statistically throughout the process, permitting their efficient removal. An exemplary application is a subranging analog-to-digital converter (ADC), in which errors associated with component digital-to-analog (DAC) current sources are discerned and corrected automatically during the circuit's normal operation. This is achieved by continually introducing a random signal into the process, statistically examining the DAC output signal to discern error terms, and correlating the occurrences of these errors with the values of the random signal applied to the DACs so as to identify the current sources to which the error terms are due. The resulting ADC output signal is compensated to remove the random signal and is further compensated to remove the DAC error terms discerned by this statistical analysis.

Abstract: A signal receiver having a frequency selective sampling detector which accepts a bandlimited analog signal and outputs uniformly spaced, digital samples of the signal's quadrature and in-phase components. The center frequency, phase reference and sample interval for the detector are derived from a single reference clock. The bandwidth of the detector is variable while maintaining the same center frequency.