Abstract: A method is provided for determining a decoupling capacitance of a device under test (DUT) interface circuitry, which is between automated testing equipment (ATE) and a DUT. The method: disconnects the DUT from the DUT interface circuitry; connects a Device Under Testing Power Supply (DPS) resource as a DUT Power Supply to the DUT interface circuitry; sets a current clamp of the DPS resource to a test application level; turns off the DPS resource voltage; sets the DPS resource to a force voltage mode; sets the current clamp to a minimum current level; turns on the output; waits a period of time to allow the decoupling capacitance to charge; places the DPS resource into a voltage measurement mode; adds any delay time to the period of time; measures the voltage before the capacitance is fully charged; and determines the decoupling capacitance.

Abstract: A method for compliance testing of a Digital Interface Board attached to Automatic Test Equipment in the testing of integrated circuit semiconductor devices using Impedance Response Profiling. The includes launching alternating voltage digital clock signals from the Pin Electronics to one or more circuit paths in the Digital Interface Board, and sampling a mix of the launched alternating voltage digital clock signals and reflected signals. The method also includes compositing time domain waveforms originating at the Pin Electronics, and generating an initial reflection response profile baseline. The method is repeated at a later predetermined time, generating a later reflection response profile. The method further includes comparing the initial reflection response profile baseline with the later reflection response profile, and determining whether the one or more circuit paths of the Digital Interface Board are in compliance with predetermined operating standards.

Abstract: A method is provided for testing the functionality of a device under test interface circuitry located between automated testing equipment (ATE) and a device under test (DUT). The method includes disconnecting the device under test from the device under test interface circuitry, utilizing a Source Measurement Unit (SMU) that generates and measures voltage and current and uses force and sense lines, and testing a switch located in the device under test interface circuitry using a two-state alarm process. The method also includes applying a voltage using the a voltage source measurement device in a first state in which force and sense lines of the voltage source measurement device are connected in the device under test interface circuitry. The method further includes detecting whether an alarm signal due to an open circuit has been activated, and determining that the switch being tested in the device under test interface circuitry is operating properly by the absence of the alarm signal being activated.

Abstract: A method is provided for in situ functionality testing of electrical switches using a Functional Reflectometry Test (FRT) of switches on the signal path of electrical circuits in a semiconductor interface. The method includes initiating the functionality testing of the electrical switches in situ, wherein the functionality of the electrical switches is tested while the electrical switches are connected to the Automatic Test Equipment (ATE) and are in-use testing semiconductors. The method also includes conducting full Functional Reflectometry Testing of the electrical switches in situ in an open switch state and a closed switch state to determine whether each of the electrical switches is one of fully functional, stuck closed, and stuck open, wherein testing for each state is performed as a single vector functional test to minimize test time overhead.

Abstract: Methods are provided that performs continuous semiconductor testing during long soak time testing using a chamberless single insertion model (SIM) handler and also using a chamberless asynchronous insertion model (AIM) handler having two manipulators. The methods include dividing a group of semiconductors having an ambient temperature into a first subgroup having a plurality of portions and a second subgroup having a plurality of portions, the second subgroup being identical to the first subgroup. The methods also include using thermal chucks to change the temperature of the first portion of the first subgroup and the first portion of a second subgroup prior to testing from ambient temperature to a stabilized designated temperature during a soak time. The methods also include testing all of the portions of the first subgroup and the second subgroup using predetermined protocols that include Soak Time, Test Time, Index Time, and sometimes Wait Time.

Abstract: A method for compliance testing of a Digital Interface Board attached to Automatic Test Equipment in the testing of integrated circuit semiconductor devices using Impedance Response Profiling. The includes launching alternating voltage digital clock signals from the Pin Electronics to one or more circuit paths in the Digital Interface Board, and sampling a mix of the launched alternating voltage digital clock signals and reflected signals. The method also includes compositing time domain waveforms originating at the Pin Electronics, and generating an initial reflection response profile baseline. The method is repeated at a later predetermined time, generating a later reflection response profile. The method further includes comparing the initial reflection response profile baseline with the later reflection response profile, and determining whether the one or more circuit paths of the Digital Interface Board are in compliance with predetermined operating standards.

Abstract: A method is provided for in situ functionality testing of electrical switches using a Functional Reflectometry Test (FRT) of switches on the signal path of electrical circuits in a semiconductor interface. The method includes initiating the functionality testing of the electrical switches in situ, wherein the functionality of the electrical switches is tested while the electrical switches are connected to the Automatic Test Equipment (ATE) and are in-use testing semiconductors. The method also includes conducting full Functional Reflectometry Testing of the electrical switches in situ in an open switch state and a closed switch state to determine whether each of the electrical switches is one of fully functional, stuck closed, and stuck open, wherein testing for each state is performed as a single vector functional test to minimize test time overhead.

Abstract: Methods are provided that performs continuous semiconductor testing during long soak time testing using a chamberless single insertion model (SIM) handler and also using a chamberless asynchronous insertion model (AIM) handler having two manipulators. The methods include dividing a group of semiconductors having an ambient temperature into a first subgroup having a plurality of portions and a second subgroup having a plurality of portions, the second subgroup being identical to the first subgroup. The methods also include using thermal chucks to change the temperature of the first portion of the first subgroup and the first portion of a second subgroup prior to testing from ambient temperature to a stabilized designated temperature during a soak time. The methods also include testing all of the portions of the first subgroup and the second subgroup using predetermined protocols that include Soak Time, Test Time, Index Time, and sometimes Wait Time.

Abstract: A method is provided for testing the functionality of a device under test interface circuitry located between automated testing equipment (ATE) and a device under test (DUT). The method includes disconnecting the device under test from the device under test interface circuitry, utilizing a Source Measurement Unit (SMU) that generates and measures voltage and current and uses force and sense lines, and testing a switch located in the device under test interface circuitry using a two-state alarm process. The method also includes applying a voltage using the a voltage source measurement device in a first state in which force and sense lines of the voltage source measurement device are connected in the device under test interface circuitry. The method further includes detecting whether an alarm signal due to an open circuit has been activated, and determining that the switch being tested in the device under test interface circuitry is operating properly by the absence of the alarm signal being activated.

Abstract: A system and method utilize a stand-alone controller for a multiplexed handler test cell in automated and robotic semiconductor test equipment for indexless tandem semiconductor testing. The stand-alone controller is configured such that functions relating to both the handler drivers and the data post-processor of the multiplexed handler tested cell are included within the stand-alone controller. The system and method also include provisions for using a virtual multiplexed handler test cell in a preliminary stage prior to actual implementation of the actual multiplexed handler test cell. This configuration permits the stand-alone controller to control the functions of the multiplexed handlers and to coordinate their activity with the tester.

Abstract: A method is provided for performing continuous single insertion semiconductor testing of a group of semiconductors that are divided into a first subgroup and a second subgroup at multiple different temperatures. The single insertion semiconductor testing is performed by sequentially executing testing cycles, characterized by the tester alternately executing temperature testing periods and temperature ramping periods for the first subgroup, while simultaneously executing temperature ramping periods and temperature testing periods for the second subgroup. The temperature testing periods operate at two or more different temperatures. The single insertion testing sequence entirely eliminates tester index time when the testing time is equal to or greater than the ramping times, and substantially reduces tester index time when the testing time is less that the ramping times.

Abstract: A modular multiplexing interface assembly and corresponding methodology are provided for reducing semiconductor testing index time in automated semiconductor test equipment using robotic handlers. The modular multiplexing interface assembly includes a modular printed circuit multiplexing motherboard that attaches to the automated semiconductor test equipment, and a plurality of modular load boards, each modular load board being detachably connected, electrically and mechanically, to a robotic handler. The modular multiplexing interface assembly also includes a plurality of electrical cable bundles, each electrical cable bundle electrically connecting the printed circuit motherboard with one of the plurality of modular load boards, wherein the plurality of electrical cable bundles are trace-length matched for a designated digital signal.

Abstract: A method is provided for performing continuous single insertion semiconductor testing of a group of semiconductors that are divided into a first subgroup and a second subgroup at multiple different temperatures. The single insertion semiconductor testing is performed by sequentially executing testing cycles, characterized by the tester alternately executing temperature testing periods and temperature ramping periods for the first subgroup, while simultaneously executing temperature ramping periods and temperature testing periods for the second subgroup. The temperature testing periods operate at two or more different temperatures. The single insertion testing sequence entirely eliminates tester index time when the testing time is equal to or greater than the ramping times, and substantially reduces tester index time when the testing time is less that the ramping times.

Abstract: A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol.

Abstract: A modular multiplexing interface assembly and corresponding methodology are provided for reducing semiconductor testing index time in automated semiconductor test equipment using robotic handlers. The modular multiplexing interface assembly includes a modular printed circuit multiplexing motherboard that attaches to the automated semiconductor test equipment, and a plurality of modular load boards, each modular load board being detachably connected, electrically and mechanically, to a robotic handler. The modular multiplexing interface assembly also includes a plurality of electrical cable bundles, each electrical cable bundle electrically connecting the printed circuit motherboard with one of the plurality of modular load boards, wherein the plurality of electrical cable bundles are trace-length matched for a designated digital signal.

Abstract: A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol.

Abstract: A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol.

Abstract: A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol.

Abstract: An electrical connector for connecting to ground and first and second signal lines includes a ground contact, a first signal contact, a second signal contact, and a switch connected to the first signal contact and the ground contact. The switch is biased “on” until after the first signal contact is connected to the first signal line, the ground contact is connected to the ground, and the second signal contact is connected to the second signal line. The switch, during connection of the connector to ground and first and second signal lines, is thereby automatically triggered to “off” during connection of the connector. If the first and second signal lines are differential signals, the switch, instead, electrically connects and disconnects the first signal contact to the second signal contact.

Abstract: A system and method utilize a stand-alone controller for a multiplexed handler test cell in automated and robotic semiconductor test equipment for indexless tandem semiconductor testing. The stand-alone controller is configured such that functions relating to both the handler drivers and the data post-processor of the multiplexed handler tested cell are included within the stand-alone controller. The system and method also include provisions for using a virtual multiplexed handler test cell in a preliminary stage prior to actual implementation of the actual multiplexed handler test cell. This configuration permits the stand-alone controller to control the functions of the multiplexed handlers and to coordinate their activity with the tester.