Abstract: Circuit designs and methods are provided for matching device characteristics for, e.g., analog or mixed-signal semiconductor integrated circuit designs. In particular, circuit layout patterns and layout methods are provided which enable precise or proportional matching of circuit components by uniformly distributing circuit components in a manner that eliminates or significantly minimizes the sensitivity of such circuit components to environmental effects and process variations, thereby improving the performance of analog and mixed-signal circuits.

Abstract: A cooling system for a semiconductor substrate incudes a plurality of trenches formed from a backside of the semiconductor substrate, and thermally conductive material deposited in the plurality of trenches. A method of forming cooling elements in a semiconductor substrate, includes coating a backside of the semiconductor substrate with a first mask layer, forming a plurality of trench patterns in the first mask layer, etching the semiconductor substrate to form a plurality of trenches along the plurality of trench patterns, and depositing thermally conductive material in the plurality of trenches. Trenches constructed from the backside of a wafer improve efficiency of heat transfer from a front-side to the backside of an integrated-circuit chip. The fabrication of trenches from the backside of the wafer allows for increases in the depth and number of trenches, and provides a means to attach passive and active cooling devices directly to the backside of a wafer.

Abstract: In accordance with the present invention, a method for producing at least two different chips with a controlled total chip thickness such that when these chips are placed into a corresponding pocket of a plurality of pockets located in a wafer chip carrier wherein each of the plurality of pockets have a total pocket depth (Tdp) at least substantially equal to one another, a substantially planarized top surface of said wafer chip carrier is achieved. The method comprises forming at least a first chip on a first dummy carrier and at least a second chip different from the first chip on a separate second dummy carrier using partial wafer bonding and partial wafer dicing.

Abstract: An apparatus, system and method of automatically computing power consumption estimation of a chip are provided. The apparatus, system and method include determining all circuit blocks or macros embedded in the chip and retrieving from a file, into which pre-generated power consumption values of the macros are stored, the power consumption value of each macro. After doing so, the power consumption value of the chip is automatically computed. The apparatus, system and method also compute a desired power consumption estimation of the chip as well as a plurality of power densities. A desired power consumption estimation is based on a desired voltage and a desired frequency while a power density is power used in a certain area. Further, the apparatus, system and method reproduces the floorplan of the chip and represents each area within the chip by a different color to illustrate hot spots and cool spots.

Abstract: Apparatus and method for providing high dielectric constant decoupling capacitors for semiconductor structures. The high dielectric constant decoupling capacitor can be fabricated by depositing high dielectric constant material between adjacent conductors on the same level, between conductors in successive levels, or both, to thereby provide very large capacitance value without any area or reliability penalty.

Abstract: An apparatus, system and method of automatically computing power consumption estimation of a chip are provided. The apparatus, system and method include determining all circuit blocks or macros embedded in the chip and retrieving from a file, into which pre-generated power consumption values of the macros are stored, the power consumption value of each macro. After doing so, the power consumption value of the chip is automatically computed. The apparatus, system and method also compute a desired power consumption estimation of the chip as well as a plurality of power densities. A desired power consumption estimation is based on a desired voltage and a desired frequency while a power density is power used in a certain area. Further, the apparatus, system and method reproduces the floorplan of the chip and represents each area within the chip by a different color to illustrate hot spots and cool spots.

Abstract: A static column redundancy scheme for a semiconductor memory such as an eDRAM. By utilizing the existing scan registers for SRAM array testing, the column redundancy information of each bank or each microcell of the memory chip can be scanned, stored and programmed during the power-on period. Two programming methods are disclosed to find the column redundancy information on the fly. In the first method, the column redundancy information is first stored in the SRAM, and is then written into the program registers of the corresponding bank or microcell location. In the second method, the column redundancy information is loaded directly into the program registers of a bank or microcell location according to the bank address information without loading the SRAM. Since the new static column redundancy scheme does not need to compare the incoming addresses, it eliminates the use of control and decoding circuits, which significantly reduces the power consumption for memory macros.

Abstract: Apparatus and method for providing high dielectric constant decoupling capacitors for semiconductor structures. The high dielectric constant decoupling capacitor can be fabricated by depositing high dielectric constant material between adjacent conductors on the same level, between conductors in successive levels, or both, to thereby provide very large capacitance value without any area or reliability penalty.