Abstract: A method and system for updating the logical address of pointers used by a processor in a paged memory organization. A logical address associative memory provides a cache holding data about a paged segment of data words eliminating the need to fetch the data from main memory. Update index logic and insertion logic operate to update the logical address of an original pointer to indicate the logical next address of new data sought from main memory. The system is specifically designed to expedite the situation where the page referenced by the next address is different from that referenced by the original pointer's address.

Abstract: An associative memory system for logical addressing of memory segments using paged memory. The physical address of a targeted data word can be generated in one machine cycle if the segment logical base address and page index of the targeted word resides in an associated set of CAMs and RAMs. If the targeted word's logical base address and page index is not in the set of associated CAMs and RAMs, this information can be acquired at the most optimum rate for enabling data access. This rate may require several clock cycles.

Abstract: A system for updating logical address data in pointers used by a processor in a computer system using paged memory. An Actual Segment Descriptor Associative Memory System (ASDAM) provides a dual cache memory for searching page table logical addresses and page index values which can, if available, provide a logical address, via a logical address RAM, to update a pointer in one machine cycle, with a new logical address. If the required data is not available in the dual cache memory, then other circuitry is operative to translate logical addresses into physical addresses permitting rapid access to main memory in order to supply the dual cache memory and logical address RAM with the required data.

Abstract: An alternate path selection structure is provided which reduces the effects of aborting an operation. The present invention comprises a structure and method that allows efficient retrieval of alternate paths to pursue in a microcode sequence.

Abstract: An address couple associateive memory (ACAM) for a processor in a chip package provides a first address couple (ACL) CAM and a second absolute address list (AAL) CAM. An associated control unit guarantees coherency of word data in a cache RAM and main memory by indicating the invalidity or validity of each location of address data in the first CAM (ACL) and second CAM (AAL). Each loaction of data words in the cache RAM is associated with a corresponding location in the first (ACL) CAM and in the second (AAL) CAM. Address translation is provided in one clock cycle when writing to a location in main memory specified by a logical address couple.

Abstract: The present invention relates to a method within a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The method includes loading the temporary storage memory with the first and second operand data strings in a pre-established order such that the subsequent fetching of the operand data words from the temporary storage memory is performed in a sequential order. The loading and fetching steps operate to achieve a desired word order such that the operation between operand data strings can be started while the operand data is being fetched.

Abstract: The present invention relates to an execution unit of a computing system which executes data manipulation type instructions and arithmetic type instructions on data words having a plurality of decimal character-type data formats. The pipelined execution unit of the present invention includes a first stage element which temporarily stores input data, the input data including operation commands defining said decimal type instructions, and input operand data. A second stage element executes a first predetermined group of the decimal type instructions. A third stage element, operatively coupled to said second stage element, executes a second predetermined group of the decimal type instructions, the second predetermined group including arithmetic type instructions.