Abstract: A field programmable gate array (FPGA) device including a configuration interface arranged to receive configuration data from an FPGA programmer. The FPGA device includes a plurality of random access memory (RAM) types, including a first RAM type and a second RAM type, arranged to store the configuration or image data. The FPGA device also includes a FIFO IP core arranged to implement a FIFO function in a plurality of different FPGA platforms. The FIFO IP core is: i) configured to implement the FIFO in the FPGA device based on the configuration data, and ii) configurable to store the configuration data in one or both of the first RAM type and the second RAM type.

Abstract: A system can include a first section with an ultra high speed digital sampler configured to sample at a first rate, a scrambler connected to the sampler, and a set of ultra high speed serial data outputs. The system can further include a second section with a set of ultra high speed serial data inputs, a set of serial to parallel converter circuits connected to the inputs and outputting data at a second rate, a descrambler having inputs connected to the reduced speed data outputs, and a set of parallel outputs configured to output the serial data. The set of ultra high speed serial data outputs of the first section are configured to be connected to the set of ultra high speed serial data inputs in the second section by a set of ultra high speed communication pathways clocked at a speed substantially equal to the first rate.

Abstract: A system can include a first section with an ultra high speed digital sampler configured to sample at a first rate, a scrambler connected to the sampler, and a set of ultra high speed serial data outputs. The system can further include a second section with a set of ultra high speed serial data inputs, a set of serial to parallel converter circuits connected to the inputs and outputting data at a second rate, a descrambler having inputs connected to the reduced speed data outputs, and a set of parallel outputs configured to output the serial data. The set of ultra high speed serial data outputs of the first section are configured to be connected to the set of ultra high speed serial data inputs in the second section by a set of ultra high speed communication pathways clocked at a speed substantially equal to the first rate.

Abstract: A system and method for designing a field programmable gate array (FPGA) with built-in test mechanism includes several enhancements to traditional circular self-test path (CSTP) BIST architecture. The FPGA BIST scheme isolates primary inputs and primary outputs to improve test coverage. Multiple signature output taps are inserted at CSTP registers throughout the test path to help improve signature aliasing probability. Enhanced CSTP register selection algorithms help prevent register adjacency problems and optimize overall resource utilization for implementation. Multiple clock domains are also handled by the FPGA BIST to allow full chip implementation of the FPGA BIST.

Abstract: A system and method for designing a field programmable gate array (FPGA) with built-in test mechanism includes several enhancements to traditional circular self-test path (CSTP) BIST architecture. The FPGA BIST scheme isolates primary inputs and primary outputs to improve test coverage. Multiple signature output taps are inserted at CSTP registers throughout the test path to help improve signature aliasing probability. Enhanced CSTP register selection algorithms help prevent register adjacency problems and optimize overall resource utilization for implementation. Multiple clock domains are also handled by the FPGA BIST to allow full chip implementation of the FPGA BIST.

Abstract: An input random access memory (RAM) module of a fast Fourier transform (FFT) engine of a DVB receiver is used to store, during a first time period, delayed versions of an input signal that includes a first orthogonal frequency division multiplexed (OFDM) symbol and a cyclic prefix therefor received at the receiver, and samples for a second OFDM symbol to be demodulated using the FFT engine during a second time period. Delayed versions of the input signal are stored in the input RAM module of the FFT engine in a first-in-first-out (FIFO) fashion for signal acquisition and for FFT processing. Similarly, an output RAM module of the FFT engine is used to store moving averages of an autocorrelation of the input signal with its cyclic prefix computed over presumed guard intervals and over multiple symbols.

Abstract: Methods and systems consistent with the present invention provide a method for dynamically controlling power consumption in a digital demodulator circuit by varying clock rates and bit widths of demodulator components including an analog to digital converter, decimation filter, OFDM operating engine, FEC decoder, and MPE-FEC processor, according to parameters and conditions of the received signal including modulation mode, signal to noise ratio, effective bit transmission rate, bit error rate, packet error rate, adjacent channel interference, and co-channel interference.