Abstract: One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.

Abstract: An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.

Abstract: An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.

Abstract: Embodiments of the present disclosure provide a feedback structure, a method of constructing a feedback structure and an integrated circuit employing the feedback structure. In one embodiment, the feedback structure is for use with an integrated circuit and includes a local interconnect configured to electrically connect an output of a CMOS inverter to another circuit in the integrated circuit. Additionally, the feedback structure also includes an interconnect extension to the local interconnect configured to proximately extend along a gate structure of the CMOS inverter to provide a reactive coupling between the output and the gate structure.

Abstract: Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, and partial dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, but where whole dummy active areas can not be accommodated. The dummy active areas are staggered so as to provide uniform parasitic capacitive coupling to overlying leads regardless of the placement of the leads. The dummy active areas are substantially evenly separated from one another by dividers. The dummy active areas and dividers are formed concurrently with formation of semiconductor devices in non-dummy active areas. The dummy active areas mitigate yield loss by, among other things, providing more uniformity across the substrate, at least with regard to parasitic capacitances and stress and subsequent processing.

Abstract: An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.

Abstract: An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.

Abstract: Embodiments of the present disclosure provide a feedback structure, a method of constructing a feedback structure and an integrated circuit employing the feedback structure. In one embodiment, the feedback structure is for use with an integrated circuit and includes a local interconnect configured to electrically connect an output of a CMOS inverter to another circuit in the integrated circuit. Additionally, the feedback structure also includes an interconnect extension to the local interconnect configured to proximately extend along a gate structure of the CMOS inverter to provide a reactive coupling between the output and the gate structure.

Abstract: Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, and partial dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, but where whole dummy active areas can not be accommodated. The dummy active areas are staggered so as to provide uniform parasitic capacitive coupling to overlying leads regardless of the placement of the leads. The dummy active areas are substantially evenly separated from one another by dividers. The dummy active areas and dividers are formed concurrently with formation of semiconductor devices in non-dummy active areas. The dummy active areas mitigate yield loss by, among other things, providing more uniformity across the substrate, at least with regard to parasitic capacitances and stress and subsequent processing.

Abstract: A method (100) of forming fully-depleted (90) and partially-depleted (92) silicon-on-insulator (SOI) devices on a single die in an integrated circuit device (2) is disclosed using SOI starting material (4, 6, 8) and a selective epitaxial growth process (110).

Abstract: A metal fuse process that uses a thinner (e.g., 6000 Å) oxide (108) over the top interconnect (102). The oxide (108) is removed over the probe pads (106) for testing but is not removed over the fuses (104). Because the oxide (108) is thin at the upper corners of the fuse (104), the oxide (108) cracks over the fuse (104) during a laser pulse (114). A wet etch is then used to dissolve the exposed fuses (104).

Abstract: According to one embodiment of the invention, a method of forming a semiconductor device is provided. The method includes providing a first mask that defines a densely populated plurality of hole patterns. The first mask overlies a layer of dielectric material. The method also includes defining at least one isolated hole pattern in the first mask by covering one or more of the defined densely populated hole patterns using a second mask. The method also includes forming a plurality of densely populated holes in the dielectric material and at least one isolated hole by etching, according to one or more of the plurality of hole patterns that are not covered by the second mask, the layer of dielectric material.

Abstract: According to one embodiment of the invention, a method of forming a semiconductor device is provided. The method includes providing a first mask that defines a densely populated plurality of hole patterns. The first mask overlies a layer of dielectric material. The method also includes defining at least one isolated hole pattern in the first mask by covering one or more of the defined densely populated hole patterns using a second mask. The method also includes forming a plurality of densely populated holes in the dielectric material and at least one isolated hole by etching, according to one or more of the plurality of hole patterns that are not covered by the second mask, the layer of dielectric material.

Abstract: A metal fuse process that uses a thinner (e.g., 6000 Å) oxide (108) over the top interconnect (102). The oxide (108) is removed over the probe pads (106) for testing but is not removed over the fuses (104). Because the oxide (108) is thin at the upper corners of the fuse (104), the oxide (108) cracks over the fuse (104) during a laser pulse (114). A wet etch is then used to dissolve the exposed fuses (104).

Abstract: A method of forming LV and HV transistors with independently optimized threshold adjust (Vt) implants to minimize reverse short channel effects. A through-the-poly implant is used for the Vt implants after gate (214) formation. The Vt implants for the LV transistors (224,226) are performed after the LDD patterns (216,238). The Vt implants for the HV transistors (220, 222) are performed after the I/O LDD patterns (234,244).

Abstract: A method of testing semiconductor wafers wherein a cassette (3) containing a plurality of semiconductor wafers for fabrication is provided. The location and orientation of each of the wafers within the cassette is determined and at least one processing step is performed on the wafers. At least one of an alteration of the location in the cassette (5) and orientation of the wafers (7) is provided and at least one additional processing step is performed on the wafers. At least one of an alteration of the location and orientation of the wafers is provided including alteration of the location or orientation of the wafers if not yet altered. At least one like parameter of each of the wafers is measured (9). The variation across the wafer of the at least one parameter is correlated with the orientation and the location on a wafer by wafer basis and processing errors are determined from the step of correlating which can be used to alter and reduce variation in the fabrication process.

Abstract: One embodiment of the present invention is a method of simultaneously forming high-voltage (12) and low-voltage (10) devices on a single substrate (14), the method comprising: forming a thin oxide layer (18) on the substrate, the thin oxide layer having a desired thickness for a gate oxide for the low-voltage device; selectively forming a gate structure (30) for the high-voltage device, the thin oxide is situated between the gate structure and the substrate; and selectively thickening the thin oxide under the gate structure while keeping the thin oxide layer utilized for the low-voltage device at the desired thickness.

Abstract: An EPROM memory cell (32) stores information in a floating gate (44) which overlies a portion of a channel between a program drain (36) and a read drain (34). A control gate (46) has a lower segment (48) which overlies the portion of the channel not covered by the floating gate (44), and has an upper portion (50) overlying the floating gate (44). During a program operation, electrons flow from the read drain (34), acting as a source, to the program drain (36), and hot electrons are stored within the floating gate (44). During a read operation, electrons flow from the programming gate (36) to the read gate (34), and the majority of hot electrons drift to the control gate (46). Since the hot electrons do not enter the floating gate (44) during read operations, a higher driving current can be used, thereby increasing the speed at which the EPROM memory cell (32) is read.

Abstract: A method of forming a metal-to-metal antifuse. An antifuse stack 32 is formed comprising a first metal layer 16, an antifuse dielectric layer, and an etchstop layer. The etchstop layer may, for example, comprise an oxide layer 24 and an amorphous silicon layer 28. An antifuse via 44 is etched through an interlevel dielectric layer 36 to the antifuse stack 32. Next, a portion of the etchstop layer at the bottom of via 44 is removed. Finally, a second layer of metal 48 is deposited to fill antifuse via 44 and etched to form the desired interconnections.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.