Abstract: According to the present invention, a domino CMOS logic circuit having a plurality of stages for evaluating logic signals is provided. In one embodiment, the domino CMOS logic circuit includes at least one stage which has a logic block that includes a plurality of logic devices, inputs and outputs, and a precharge/evaluate circuit. In a more specific embodiment, the circuit includes a first transistor having a source connected to a supply voltage, a gate connected to a delayed clock signal, and a drain, a second transistor having a source connected to the drain of the first transistor, a gate connected to a clock signal, and a drain connected to the outputs of the logic block.