Patents by Inventor Howard Lee Marks

Howard Lee Marks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8951814
    Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: February 10, 2015
    Assignee: NVIDIA Corporation
    Inventors: Brian S. Schieck, Howard Lee Marks
  • Patent number: 8357931
    Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: January 22, 2013
    Assignee: Nvidia Corporation
    Inventors: Brian S. Schieck, Howard Lee Marks
  • Patent number: 8017520
    Abstract: An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer may define a frame with an outer periphery and an inner periphery.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: September 13, 2011
    Assignee: NVIDIA Corporation
    Inventors: Inderjit Singh, Howard Lee Marks, Joseph David Greco
  • Patent number: 7842948
    Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: November 30, 2010
    Assignee: NVIDIA Corporation
    Inventors: Brian S. Schieck, Howard Lee Marks
  • Patent number: 7791193
    Abstract: An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer is meshed.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: September 7, 2010
    Assignee: NVIDIA Corporation
    Inventors: Inderjit Singh, Howard Lee Marks, Joseph David Greco
  • Patent number: 7649269
    Abstract: An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer may define a frame with an outer periphery and an inner periphery.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: January 19, 2010
    Assignee: NVIDIA Corporation
    Inventors: Inderjit Singh, Howard Lee Marks, Joseph David Greco
  • Patent number: 7495343
    Abstract: An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer may define a frame with an outer periphery and an inner periphery.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: February 24, 2009
    Assignee: NVIDIA Corporation
    Inventors: Inderjit Singh, Howard Lee Marks, Joseph David Greco
  • Patent number: 7453158
    Abstract: An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer is meshed.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: November 18, 2008
    Assignee: NVIDIA Corporation
    Inventors: Inderjit Singh, Howard Lee Marks, Joseph David Greco
  • Patent number: 7429528
    Abstract: An integrated circuit and method of fabricating the same are provided. Included are an active circuit, and a metal layer disposed, at least partially, above the active circuit. Further provided is a bond pad disposed, at least partially, above the metal layer. To prevent damage incurred during a bonding process, the aforementioned metal layer is meshed.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: September 30, 2008
    Assignee: NVIDIA Corporation
    Inventors: Inderjit Singh, Howard Lee Marks, Joseph David Greco
  • Publication number: 20080128695
    Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.
    Type: Application
    Filed: December 28, 2007
    Publication date: June 5, 2008
    Inventors: Brian S. Schieck, Howard Lee Marks