Abstract: In a described example, an automated fluid pumping system (AFPS) includes a fluid pump coupled to a pump controller, an electronic sensor that detects air, oil, or water coupled to a sensor controller, and the sensor controller coupled to the pump controller. The pump controller is configured to control the operation of the fluid pump based on a detected fluid in the well as determined by the electronic sensor.

Abstract: A semiconductor device includes a gate electrode having ends that overlap isolation regions, wherein the gate electrode is located over an active region located within a semiconductor substrate. A gate oxide is located between the gate electrode and the active regions, and source/drains are located adjacent the gate electrode and within the active region. An etch stop layer is located over the gate electrode and the gate electrode has at least one electrical contact that extends through the etch stop layer and contacts a portion of the gate electrode that in one embodiment overlies the active region, and in another embodiment is less than one alignment tolerance from the active region.

Abstract: One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.

Abstract: A silicon on insulator (SOI) multi-gate field effect transistor electrically Programmable Read-Only Memory (MuFET EPROM) includes a substrate having a dielectric surface. A first semiconducting region is in or on the dielectric surface. A source region, a drain region and a channel region interposed between the source and drain are formed in first semiconducting region. A gate dielectric layer is on the channel region. At least a second semiconducting region in or on the dielectric surface is spaced apart from the first semiconducting region. A first electrode layer comprises a first electrode portion including a transistor gate electrode and a control gate electrode electrically isolated from one another. The transistor gate overlies the channel region to form a transistor. The control gate extends to overlay a portion of the second semiconducting region.

Abstract: One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.

Abstract: One embodiment of the present invention relates to an integrated circuit that includes a memory cell. The memory cell includes a capacitor configured to store a charge or voltage. The capacitor includes a first semiconductor fin having a first conductivity type and overlying a semiconductor body, a dielectric overlying at least part of the semiconductor fin, and a gate electrode overlying the dielectric. The memory cell also includes a diode. The diode includes an end portion of the first semiconductor fin and a second semiconductor fin that forms a junction with the end portion of the first semiconductor fin. The second semiconductor fin has a second conductivity type and includes first and second legs in different directions from the junction. Other devices and methods are also disclosed.

Abstract: One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.

Abstract: In one aspect provides a semiconductor device that includes gate electrodes having ends that overlap isolation regions, wherein each gate electrode] is located over an active region located within a semiconductor substrate. A gate oxide is located between each of the gate electrodes and the active region, and source/drains are located adjacent each of the gate electrodes and within the active region. An etch stop layer is located over each of the gate electrodes and each of the gate electrodes has at least one electrical contact that extends through the etch stop layer and contacts a portion of the gate electrode that overlies the active region.

Abstract: An integrated circuit having fully-depleted silicon-on-insulator (FD-SOI) transistors and partially-depleted silicon-on-insulator (PD-SOI) transistors on a semiconductor substrate is disclosed.

Abstract: An integrated circuit having fully-depleted silicon-on-insulator (FD-SOI) transistors and bulk transistors on a semiconductor substrate is disclosed.

Abstract: A method (10) of forming fully-depleted silicon-on-insulator (FD-SOI) transistors (150) and partially-depleted silicon-on-insulator (FD-SOI) transistors (152) on a semiconductor substrate (104) as part of an integrated circuit fabrication process is disclosed.

Abstract: A method (10) of forming fully-depleted silicon-on-insulator (FD-SOI) transistors (150) and bulk transistors (152) on a semiconductor substrate (104) as part of an integrated circuit fabrication process is disclosed.

Abstract: Semiconductor devices (102) are presented along with fabrication methods (202) therefor, in which a conductive contact structure (116b) is formed with a lower contact surface (116c) having a lateral contact dimension (152), where the contact structure (116b) is at least partially coupled with a contact landing surface of a polysilicon structure (110) having a lateral contact landing surface dimension (150) that is less than about 140% of the lateral contact dimension (152) of the conductive contact structure (116b).

Abstract: A gate structure (30) is formed on a semiconductor (10). Source and drain extension regions (130) are formed in the semiconductor (10) adjacent to the gate structure (30). Metal silicide layers (140) are formed on the extension regions (130) and sidewall structures (155, 165, and 175) are formed over the metal silicide layers (140). Source and drain regions (120) are formed in the semiconductor (10), and metal silicide layers (180) are formed on the source and drain regions (120).