Patents by Inventor Howard Lin

Howard Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240319261
    Abstract: An example system is for testing a device under test (DUT) that includes a first core and a second core. The system includes channels in parallel for connecting to a number of pins on the DUT. The channels are for sending test data to the DUT and for receiving measurement data from the DUT based on the test data. The measurement data includes time-division-multiplexed (TDM) data comprised of successive data packets received from the DUT over the channels as part of a bitstream. Each data packet includes a first number of bits from the first core and a second number of bits from the second core. Circuitry associated with the channels is configured to compare the measurement data with expected data, and to determine pass/fail status for the first core and for the second core based on the comparison.
    Type: Application
    Filed: March 21, 2023
    Publication date: September 26, 2024
    Inventors: Howard Lin, Michael C. Panis
  • Patent number: 12008234
    Abstract: An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (DUT) to be tested.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: June 11, 2024
    Assignee: TERADYNE, INC.
    Inventors: Scott D. Schaber, Howard Lin
  • Publication number: 20240130160
    Abstract: A tandem OLED display is provided, including a substrate backplane, an anode layer, at least two stacked OLED layers, each OLED layer comprising a plurality of pixels, at least one charge generation layer (CGL), wherein each CGL is disposed between two adjacent stacked OLED layers, and a cathode layer. At least one of the CGLs is patterned wherein a pattern provides gaps between each of the plurality of pixels.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 18, 2024
    Inventors: Fangchao ZHAO, Howard LIN, Ilyas I. KHAYRULLIN, Kerry TICE, Timothy CONSIDINE, Laurie SZIKLAS, Amalkumar P. GHOSH
  • Publication number: 20240121977
    Abstract: A tandem OLED device is provided, including an anode, a cathode, at least two electroluminescent units disposed between the anode and the cathode, and an alloy thin film disposed between the two electroluminescent units.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 11, 2024
    Inventors: Fangchao ZHAO, Howard LIN, Ilyas I. KHAYRULLIN, Kerry TICE, Timothy CONSIDINE, Laurie SZIKLAS, Amalkumar P. GHOSH
  • Publication number: 20240081136
    Abstract: Systems and methods for performing direct patterning of a material on a substrate with high fidelity to a desired pattern are presented. A pattern of apertures of a shadow mask is compensated to accommodate a range of propagation angles in a vapor plume used to deposit material onto the substrate through the shadow mask. A shadow mask in accordance with the present disclosure includes an aperture pattern in which aperture position is shifted inward toward the center of the shadow mask by an amount based on the distance of the aperture from the center of the shadow mask. As a result, vaporized material passing through an aperture at a non-normal angle deposits onto the substrate at its proper desired location.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Inventors: Ilyas I. KHAYRULLIN, Howard LIN, Fangchao ZHAO, Timothy CONSIDINE, Laurie SZIKLAS, Kerry TICE, Amalkumar P. GHOSH
  • Publication number: 20240081135
    Abstract: A direct patterning deposition mask for OLED deposition is provided where the mask includes a sapphire substrate; and a Silicon Nitride (SiN) membrane. The sapphire substrate thickness may be between 0.7 and 2 mm. The sapphire substrate may have a diameter in the range of 200 mm diameter to 300 mm diameter. Warpage of the substrate is preferably less than <10 um.
    Type: Application
    Filed: August 21, 2023
    Publication date: March 7, 2024
    Inventors: Amalkumar P. GHOSH, Howard LIN, Fridrich VAZAN, Ilyas I. KHAYRULLIN, Fangchao ZHAO, Kerry TICE, Timothy CONSIDINE, Laurie SZIKLAS
  • Publication number: 20240042482
    Abstract: A system for deposition of evaporated material on a substrate is provided. The substrate has a central axis. The system includes an evaporation vacuum chamber, at least one nozzle assembly, and a shadow mask. The nozzle assembly has a three-point plurality of point evaporation sources disposed adjacent to the central axis of the substrate and at a distance from the substrate whereby the nozzle assembly provides for molecules of evaporated material to arrive at the substrate at an incident angle of less than or equal to 5 degrees.
    Type: Application
    Filed: August 3, 2023
    Publication date: February 8, 2024
    Inventors: Fridrich VAZAN, Ilyas I. KHAYRULLIN, Howard LIN, Fangchao ZHAO, Kerry TICE, Timothy CONSIDINE, Laurie SZIKLAS, Maxim FRAYER, Amalkumar P. GHOSH, Tim BRAUN
  • Publication number: 20230146534
    Abstract: An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (DUT) to be tested.
    Type: Application
    Filed: November 10, 2021
    Publication date: May 11, 2023
    Inventors: Scott D. Schaber, Howard Lin
  • Patent number: 9824608
    Abstract: A method for visually guided storage array installation is disclosed. The method includes receiving an installation plan for a storage array and determining a component of the storage array that is specified in the installation plan. One or more visual indicators that are associated with the component of the storage array are displayed to indicate a status corresponding to executing a portion of the installation plan.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: November 21, 2017
    Assignee: Pure Storage, Inc.
    Inventor: Howard Lin
  • Publication number: 20170084680
    Abstract: Embodiments provided herein describe methods and systems for forming high-k dielectric materials, as well as devices that utilize such materials. A property of a high-k dielectric material is selected. A value of the selected property of the high-k dielectric material is selected. A chemical composition of the high-k dielectric material is selected from a plurality of chemical compositions of the high-k dielectric material. The selected chemical composition of the high-k dielectric material includes an amount of nitridation associated with the selected value of the selected property of the high-k dielectric material. The high-k dielectric material is formed with the selected chemical composition.
    Type: Application
    Filed: September 14, 2016
    Publication date: March 23, 2017
    Applicant: Intermolecular, Inc.
    Inventors: Howard Lin, Gaurav Saraf, Kiet Vuong
  • Publication number: 20170084643
    Abstract: Embodiments provided herein describe storage capacitors for active matrix displays and methods for making such capacitors. A substrate is provided. A bottom electrode is formed above the substrate. A dielectric layer is formed above the bottom electrode. A top electrode is formed above the dielectric layer. A layer including an amorphous or crystalline material may be formed between the dielectric layer and the top electrode. The bottom electrode may have a thickness of at least 1000 ?, be formed in a gaseous environment of at least 95% argon, and/or not undergo an annealing process before the formation of a dielectric layer above the bottom electrode. The dielectric layer may include a nitrided high-k dielectric material.
    Type: Application
    Filed: September 14, 2016
    Publication date: March 23, 2017
    Applicant: Intermolecular, Inc.
    Inventors: Gaurav Saraf, Howard Lin, Prashant Phatak, Sang Lee, Minh Huu Le, Hieu Pham, Congwen Yi
  • Patent number: 9279857
    Abstract: A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: March 8, 2016
    Assignee: Teradyne, Inc.
    Inventors: Howard Lin, Corbin L. Champion, Jan Paul Anthonie van der Wagt, Ronald A. Sartschev
  • Publication number: 20150137838
    Abstract: A semiconductor device-under-test (DUT) may be tested by an automated test system that processes test programs specifying a number of edges per tester cycle that may be greater than the number of edges the tester is capable of generating. The test system may include circuitry that reduces the number of edges in each cycle of a test program based on data specifying operation of the tester in that cycle and/or a prior cycle. Such a reduction simplifies the circuitry required to implement an edge generator by reducing the total number of timing verniers per channel. Nonetheless, flexibility in programming the test system is retained.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: Teradyne, Inc.
    Inventors: Howard Lin, Corbin L. Champion, Jan Paul Anthonie van der Wagt, Ronald A. Sartschev
  • Patent number: 6786636
    Abstract: A mechanism for removing probe covers from an ear thermometer includes a fastening portion, a connecting portion and a pushing portion. The fastening portion is mounted to the thermometer at a portion near the measuring probe. The connecting portion has one end connected to the fastening portion and the other end connected to the pushing portion. The pushing portion is located at rear end of the probe cover so that as the connecting portion or the pushing portion being pressed by user, the probe cover is removed from the probe.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: September 7, 2004
    Assignee: Norm Pacific Automation Corp.
    Inventors: Hung-Tsan Huang, Min-Teng Chu, Howard Lin
  • Publication number: 20040153006
    Abstract: Intracorporeal and other elongate medical devices such as guidewires, catheters and the like can be formed with an ionomeric polymer sleeve or jacket covering at least a portion of the elongate medical device to form a hydrophilic surface thereon. The ionomeric polymer sleeve or jacket can be hydrophilic and can eliminate the need for subsequent application of a traditional hydrophilic coating such as a hydrogel.
    Type: Application
    Filed: February 3, 2003
    Publication date: August 5, 2004
    Applicant: SciMed Life Systems, Inc.
    Inventors: Anthony C. Vrba, Horng-Ban (Howard) Lin
  • Patent number: D534160
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: December 26, 2006
    Assignee: Gigalumen Technology Corp.
    Inventors: Howard Lin, Cheng-Hung Peng