Abstract: A method and system for maintaining computer network security allows for changeable encryption keys used by each individual work station to be looked up by a server. The server will have numerous logical interfaces corresponding to the active encryption keys, and information is routed through the appropriate interface depending upon which work station is communicating with the server. Each encryption key is encrypted into a transport key for transmission as part of each information packet.

Abstract: A system for teleconferencing presentations by a presenter is disclosed, including a cart forming a podium, a computer in or on the cart, a touch panel interface with the computer, positioned on the cart, visible to the presenter; and a CODEC operationally attached to the computer. One arrangement includes a first camera for taking a video image of the presenter, mounted on the cart, and a second camera, mounted on the cart, for taking images of documents. In one preferred arrangement, the system also includes a projector associated with the cart and a screen. The projector projects images from the first or second camera to the screen.

Abstract: There is disclosed a method and system for determining the progress of a calling connection. The system measures the peak voltage of the signals on the line and derives a ratio of these peak signals to the average value of the signal. From this ratio a determination is made as to the calling condition of the line.

Abstract: A high speed computer system has a high speed processor for executing program sequences in a single fetch cycle; an instruction memory means for communicating with the high speed processor; a data memory for communicating with the high speed processor and a special subroutine handling operation which is implemented through a picosequencer which provides for interrupting the program, loading the contents of the instructions being implemented into a memory, executing the subroutine under the control of a picosequencer and then returning to the operation of the program.

Abstract: A high speed data processor obtains its speed through the efficient transfer of information over separate data and instruction busses, prefetching of instructions, dual working memory and architectural arrangements designed for maximum information transfer. The architecture of the data processor is such that data from any of several sources may be, either in combination or separately, channelled directly through an Arithmetic Logic Unit (ALU) so as to provide quick manipulation of the data since no extra iterations are needed in this movement. The processor uses two scratch pad or working memory areas. Both scratch pad memories communicate directly with the ALU so as to provide two operands, one from each memory and for the operation of the ALU. Two independent registers are provided which allow the linkage of computer words to obtain longer words thereby and a resulting higher precision. This linkage is accomplished by mapping and carrying the most significant bit over to the next sequentially mapped word.