Patents by Inventor Howard S. Goad

Howard S. Goad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5472774
    Abstract: A photolithography test structure is provided for measuring the amount of notching associated with photolithography processing. The test structure includes a curved insulating structure placed in close spaced proximity with a conductive, interconnect structure. A pair of conductive pads are deposited at opposite ends of the interconnect structure for measuring the resistance through the interconnect. Depending upon the amount of notching associated with the interconnect, resistance readings will vary. Test areas containing notched interconnect can be compared with controlled areas specifically designed not to have notching in order to determine relative changes in resistance, and to correlate that resistance with notching magnitude. The insulating structure, interconnect structure and conductive pads are processed upon the same substrate material containing the resulting product requiring testing.
    Type: Grant
    Filed: August 19, 1994
    Date of Patent: December 5, 1995
    Assignee: Advanced Micro Devices
    Inventors: Howard S. Goad, Derick J. Wristers, James H. Hussey, Jr., Michael A. Hillis, William C. Chapman
  • Patent number: 5370923
    Abstract: A photolithography test structure is provided for measuring the amount of notching associated with photolithography processing. The test structure includes a curved insulating structure placed in close spaced proximity with a conductive, interconnect structure. A pair of conductive pads are deposited at opposite ends of the interconnect structure for measuring the resistance through the interconnect. Depending upon the amount of notching associated with the interconnect, resistance readings will vary. Test areas containing notched interconnect can be compared with controlled areas specifically designed not to have notching in order to determine relative changes in resistance, and to correlate that resistance with notching magnitude. The insulating structure, interconnect structure and conductive pads are processed upon the same substrate material containing the resulting product requiring testing.
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: December 6, 1994
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Howard S. Goad, Derick J. Wristers, James H. Hussey, Jr., Michael A. Hillis, William C. Chapman