Abstract: A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions.

Abstract: A method of forming a mask. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method further includes (i) creating a cluster of P representative dummy features, P being a positive integer less than N, (ii) performing OPC for the cluster of the P representative dummy features but not for the N original dummy features, resulting in P OPC-applied representative dummy features, and (iii) forming the mask including N mask dummy features. The N mask dummy features are identical. Each mask dummy feature of the N mask dummy features of the mask has an area which is a function of at least an area of an OPC-applied representative dummy feature of the P OPC-applied representative dummy features. The N mask dummy features have the same relative positions as the N original dummy features.

Abstract: Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the buried oxide layer of the SOI substrate.

Abstract: Methods and structures for improving substrate loss and linearity in SOI substrates. The methods include forming damaged crystal structure regions under the buried oxide layer of SOI substrates and the structures included damaged crystal structure regions under the buried oxide layer of the SOI substrate.

Abstract: A method of forming a mask. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method further includes (i) creating a cluster of P representative dummy features, P being a positive integer less than N, (ii) performing OPC for the cluster of the P representative dummy features but not for the N original dummy features, resulting in P OPC-applied representative dummy features, and (iii) forming the mask including N mask dummy features. The N mask dummy features are identical. Each mask dummy feature of the N mask dummy features of the mask has an area which is a function of at least an area of an OPC-applied representative dummy feature of the P OPC-applied representative dummy features. The N mask dummy features have the same relative positions as the N original dummy features.

Abstract: A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions.

Abstract: A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, (b) N semiconductor regions on the substrate, and (c) P semiconductor regions on the substrate, N and P being positive integers. The N semiconductor regions comprise dopants. The P semiconductor regions do not comprise dopants. The structure further includes M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer. The M interconnect layers include an inductor. (i) The N semiconductor regions do not overlap and (ii) the P semiconductor regions overlap the inductor in the reference direction. A plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions.

Abstract: Structures and methods for forming the same. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method further includes (i) creating a cluster of P representative dummy features, P being a positive integer less than N, (ii) performing OPC for the cluster of the P representative dummy features but not for the N original dummy features, resulting in P OPC-applied representative dummy features, and (iii) forming the mask including N mask dummy features. The N mask dummy features are identical. Each mask dummy feature of the N mask dummy features of the mask has an area which is a function of at least an area of an OPC-applied representative dummy feature of the P OPC-applied representative dummy features. The N mask dummy features have the same relative positions as the N original dummy features.

Abstract: A structure and a method for forming the same. The structure includes (a) a substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface, (b) N semiconductor regions on the substrate, and (c) P semiconductor regions on the substrate, N and P being positive integers. The N semiconductor regions comprise dopants. The P semiconductor regions do not comprise dopants. The structure further includes M interconnect layers on top of the substrate, the N semiconductor regions, and the P semiconductor regions, M being a positive integer. The M interconnect layers include an inductor. (i) The N semiconductor regions do not overlap and (ii) the P semiconductor regions overlap the inductor in the reference direction. A plane perpendicular to the reference direction and intersecting a semiconductor region of the N semiconductor regions intersects a semiconductor region of the P semiconductor regions.

Abstract: Structures and methods for forming the same. The method includes providing design information of a design layer. The design layer includes M original design features and N original dummy features. The method further includes (i) creating a cluster of P representative dummy features, P being a positive integer less than N, (ii) performing OPC for the cluster of the P representative dummy features but not for the N original dummy features, resulting in P OPC-applied representative dummy features, and (iii) forming the mask including N mask dummy features. The N mask dummy features are identical. Each mask dummy feature of the N mask dummy features of the mask has an area which is a function of at least an area of an OPC-applied representative dummy feature of the P OPC-applied representative dummy features. The N mask dummy features have the same relative positions as the N original dummy features.

Abstract: Crystal lattice dislocations in material surrounding trench capacitors and other trench structures are avoided by alteration of stresses such as decreasing compressive stresses and/or development of persistent tensile forces within material deposited in the trench and thus at the material interface formed by the trench. Such alteration of stresses is achieved by volume reduction of a film deposited in the trench. The material is preferably a hydrogenated nitride of silicon, boron or silicon-carbon alloy which may be reduced in volume by partial or substantially complete dehydrogenation during subsequent heat treatment at temperatures where the film will exhibit substantial creep resistance. The amount of volume reduction can be closely controlled by control of concentration of hydrogen or other gas or volatile material in the film.

Abstract: Crystal lattice dislocations in material surrounding trench capacitors and other trench structures are avoided by alteration of stresses such as decreasing compressive stresses and/or development of persistent tensile forces within material deposited in the trench and thus at the material interface formed by the trench. Such alteration of stresses is achieved by volume reduction of a film deposited in the trench. The material is preferably a hydrogenated nitride of silicon, boron or silicon-carbon alloy which may be reduced in volume by partial or substantially complete dehydrogenation during subsequent heat treatment at temperatures where the film will exhibit substantial creep resistance. The amount of volume reduction can be closely controlled by control of concentration of hydrogen or other gas or volatile material in the film.