Patents by Inventor Howard T. Barrett

Howard T. Barrett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7448017
    Abstract: A method and system is provided to use the same design manipulation processes for both chip design and kerf design. Concurrent generation of kerf designs and chip designs provides a consistent, accurate, and repeatable process. Improved quality of wafer testing results because the data in the kerf matches data in the chip. The total cycle time for mask manufacturing is reduced because kerf build is accomplished prior to start of the mask manufacturing process. Also provided is the use of load balancing across multiple servers during kerf and chip design to optimize computing resources.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: November 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Howard T. Barrett, Pierre J. Bouchard, James B. Clairmont, Karen S. Edwards, Maureen F. McFadden, John F. Rudden, Jr., Florence Marie St. Pierre Sears, Jeffrey C. Stamm
  • Patent number: 7275234
    Abstract: A method and system is provided to use the same design manipulation processes for both chip design and kerf design. Concurrent generation of kerf designs and chip designs provides a consistent, accurate, and repeatable process. Improved quality of wafer testing results because the data in the kerf matches data in the chip. The total cycle time for mask manufacturing is reduced because kerf build is accomplished prior to start of the mask manufacturing process. Also provided is the use of load balancing across multiple servers during kerf and chip design to optimize computing resources.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: September 25, 2007
    Assignee: International Business Machines Corporation
    Inventors: Howard T. Barrett, Pierre J. Bouchard, James B. Clairmont, Karen S. Edwards, Maureen F. McFadden, John F. Rudden, Jr., Florence Marie St. Pierre Sears, Jeffrey C. Stamm
  • Patent number: 6417515
    Abstract: A substrate, such as a semiconductor chip or wafer, is implanted along with product wafers in an ion implant vacuum system. The substrate is then annealed in an annealing step that is accomplished while the substrate is within the vacuum system. The annealer is a rapid thermal annealer, such as a laser annealer or a flash lamp annealer. The annealing step does not affect the product wafers. Then a measurement is performed on the implanted and annealed substrate while it is within the vacuum system that can be suitably correlated with implant dose. The measurement can be with a technique such as a four point probe or with a tool that measures optical reflectivity from a surface of the implanted substrate. An additional implant can then be provided to product wafers if necessary to come closer to the desired dose.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: July 9, 2002
    Assignee: International Business Machines Corporation
    Inventors: Howard T. Barrett, John J. Ellis-Monaghan, Toshiharu Furukawa, James A. Slinkman