Abstract: A surgical filament snare assembly including an anchor capable of being fixated in bone and having a filament engagement feature. A first filament has a noose with first and second noose limbs connected, preferably slidably, to the filament engagement feature. The first and second noose limbs emerge from the anchor as first and second free filament limbs that are capable of being passed through tissue to be repaired and then passable through the noose. The noose is capable of receiving the free filament limbs and strangulating them when tension is applied to at least one of the free filament limbs and the noose to enable incremental tensioning of the tissue after anchor fixation. Preferably, the snare assembly further includes a flexible sleeve joining at least some portion of the first and second free filament limbs to facilitate passing of the free filament limbs as a single unit.

Abstract: A surgical filament snare assembly including an anchor capable of being fixated in bone and having a filament engagement feature. A first filament has a noose on a first portion of at least a first limb and has a second portion connected to the filament engagement feature of the anchor. Preferably, at least one free filament limb, which in some embodiments is a length of the first filament and in other embodiments is a second filament, is capable of being passed through tissue to be repaired and has at least one end passable through the noose to enable incremental tensioning of the tissue after the anchor is fixated in bone. The noose strangulates the free filament limb when tension is applied to at least one of the free filament limb and the noose.

Abstract: Methods for passing multiple sutures through tissue are provided herein. In particular, the methods described herein allow multiple sutures to be passed through tissue without removing a suture passing instrument from a patient's body. In one embodiment, a method for passing a suture through tissue is provided that includes loading first and second suture limbs into a suture passing instrument, positioning the instrument within a patient's body, actuating the instrument to pass a portion of the first suture limb through the tissue, pulling the first suture limb through the tissue, pulling the second suture limb to reload the suture passing instrument without removing the instrument from the patient's body, actuating the instrument a second time to pass a portion of the second suture limb through the tissue, and pulling the second suture limb through the tissue.

Abstract: A delay circuit for an RFID tag includes a power supply input and a power supply output and one or more delay circuits in cascade connection between the power supply input and the power supply output. A first delay circuit includes a passive circuit, a second delay circuit includes a ramp circuit, and a third delay circuit includes a current mirror circuit.

Abstract: A clamp circuit for an RFID tag includes a power supply node, a dynamic clamp coupled between the power supply node and ground, and an active clamp coupled between the power supply and ground, having a shunt combined effect for providing a clamped power supply node VDDR voltage. The dynamic clamp includes a capacitor divider circuit, a resistor coupled to the capacitor divider circuit, and an N-channel transistor coupled to the capacitor divider circuit. The active clamp includes a differential amplifier having a first input coupled to a resistor divider, a second input for receiving a reference voltage, and an output coupled to a P-channel transistor for the clamped VDDR voltage.

Abstract: Sequencing circuitry for a ferroelectric RFID circuit includes an input node for receiving an external voltage, a bandgap circuit coupled to the input node, a bandgap ready circuit coupled to the bandgap circuit, a slew filter having an input coupled to the input node and to the bandgap ready circuit, a filter capacitor coupled to an output of the slew filter, and an LDO regulator having an input coupled to the output of the slew filter having a plurality of regulated voltages for use in a memory portion, a digital circuit portion, and for generating a reset signal. The sequencing circuitry further includes delay circuits for introducing a controlled delay between operational modes, POR cells for monitoring power supply voltages, and a digital state machine for monitoring internal nodes to control a shut-down pulse generator.

Abstract: A delay circuit for an RFID tag includes a power supply input and a power supply output and one or more delay circuits in cascade connection between the power supply input and the power supply output. A first delay circuit includes a passive circuit, a second delay circuit includes a ramp circuit, and a third delay circuit includes a current mirror circuit.

Abstract: In one embodiment, a programmable logic device includes configuration memory, an SPI port for receiving a bitstream, a chip select output pin, and configuration control circuitry. The chip select output pin can provide a chip select signal having a first logic state for selecting another device (such as another PLD) to receive a bitstream and a second logic state for de-selecting the other device. The configuration control circuitry is responsive to a command embedded in the received bitstream to drive the chip select output pin from the second logic state to the first logic state, thereby selecting the other device to receive the bitstream. Several such PLDs connected in a daisy chain can thus be configured from a single configuration source or have their configuration data read back while so connected.

Abstract: Sequencing circuitry for a ferroelectric RFID circuit includes an input node for receiving an external voltage, a bandgap circuit coupled to the input node, a bandgap ready circuit coupled to the bandgap circuit, a slew filter having an input coupled to the input node and to the bandgap ready circuit, a filter capacitor coupled to an output of the slew filter, and an LDO regulator having an input coupled to the output of the slew filter having a plurality of regulated voltages for use in a memory portion, a digital circuit portion, and for generating a reset signal. The sequencing circuitry further includes delay circuits for introducing a controlled delay between operational modes, POR cells for monitoring power supply voltages, and a digital state machine for monitoring internal nodes to control a shut-down pulse generator.

Abstract: A shunt regulator for an RFID tag chip is powered from split outputs from the RF rectifier, including a first output for providing a power delivery path to on-chip circuits and a second output for providing a discharge-regulation path. The shunt regulator includes a capacitor coupled between the first output and ground. The shunt regulator further includes an input node for receiving a power supply voltage from the rectifier split outputs, a first diode having an anode coupled to the input node, a second diode having an anode coupled to the input node, a resistor divider circuit and amplifier coupled between a cathode of the first diode and ground, transistor having a control terminal coupled to an output of the resistor divider and amplifier circuit, and a current path coupled between a cathode of the second diode and ground.

Abstract: A clamp circuit for an RFID tag includes a power supply node, a dynamic clamp coupled between the power supply node and ground, and an active clamp coupled between the power supply and ground, having a shunt combined effect for providing a clamped power supply node VDDR voltage. The dynamic clamp includes a capacitor divider circuit, a resistor coupled to the capacitor divider circuit, and an N-channel transistor coupled to the capacitor divider circuit. The active clamp includes a differential amplifier having a first input coupled to a resistor divider, a second input for receiving a reference voltage, and an output coupled to a P-channel transistor for the clamped VDDR voltage.

Abstract: A surgical filament snare assembly including an anchor capable of being fixated in bone and having a filament engagement feature. A first filament has a noose with first and second noose limbs connected, preferably slidably, to the filament engagement feature. The first and second noose limbs emerge from the anchor as first and second free filament limbs that are capable of being passed through tissue to be repaired and then passable through the noose. The noose is capable of receiving the free filament limbs and strangulating them when tension is applied to at least one of the free filament limbs and the noose to enable incremental tensioning of the tissue after anchor fixation. Preferably, the snare assembly further includes a flexible sleeve joining at least some portion of the first and second free filament limbs to facilitate passing of the free filament limbs as a single unit.

Abstract: A surgical filament snare assembly including an anchor capable of being fixated in bone and having a filament engagement feature. A first filament has a noose on a first portion of at least a first limb and has a second portion connected to the filament engagement feature of the anchor. Preferably, at least one free filament limb, which in some embodiments is a length of the first filament and in other embodiments is a second filament, is capable of being passed through tissue to be repaired and has at least one end passable through the noose to enable incremental tensioning of the tissue after the anchor is fixated in bone. The noose strangulates the free filament limb when tension is applied to at least one of the free filament limb and the noose.

Abstract: A surgical filament snare assembly including an anchor capable of being fixated in bone and having a filament engagement feature. A first filament has a noose with first and second noose limbs connected, preferably slidably connected, to the filament engagement feature of the anchor. The first and second noose limbs emerge from the anchor as first and second free filament limbs which are capable of being passed through tissue to be repaired and then passable through the noose. The noose, such as one or more half-hitches, is capable of receiving the free filament limbs and strangulating them when tension is applied to at least one of the free filament limbs and the noose to enable incremental tensioning of the tissue after the anchor is fixated. Preferably, the snare assembly further includes a flexible sleeve joining at least some portion of the first and second free filament limbs to facilitate passing of the free filament limbs at least through the tissue as a single unit.

Abstract: In one embodiment, a method of verifying a programming operation of a programmable logic device includes storing in non-volatile memory within the programmable logic device configuration data and a pre-calculated code value based on the configuration data. The method further includes transferring the configuration data from non-volatile memory to configuration memory within the programmable logic device; calculating a code value based on the configuration data transferred from the non-volatile memory to the configuration memory; and comparing the calculated code value to the pre-calculated code value.

Abstract: Various techniques are described to provide an internally triggered reconfiguration of a programmable logic device (PLD). In one example, a PLD includes configuration memory adapted to store first configuration data to configure the PLD for its intended function. The PLD also includes a bus interface adapted to interface with configuration data storage memory. The PLD further includes user logic configured by the first configuration data and adapted to provide a reconfiguration signal to trigger a reconfiguration of the PLD. In addition, the PLD includes a bus interface controller responsive to the reconfiguration signal for loading second configuration data from the configuration data storage memory via the bus interface.

Abstract: In one embodiment of the invention, a programmable logic device includes configuration memory and a controller. The controller can read a first bitstream from a first memory block of non-volatile memory and detect whether the first bitstream contains a valid preamble as the first bitstream is read from the non-volatile memory and before configuration data in the first bitstream is programmed into the volatile configuration memory. If a valid preamble is detected in the first bitstream, the controller programs the configuration memory with configuration data in the first bitstream. If a valid preamble is not detected in the first bitstream, the controller reads a second bitstream from a second memory block of the non-volatile memory.

Abstract: In one embodiment, a programmable logic device includes a plurality of logic blocks; a plurality of input/output blocks; volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks; embedded block RAM adapted to store user data; flash memory having at least a first partition and a second partition; and a data port adapted to provide external device access to the first partition of the non-volatile memory. The flash memory is adapted to store within the first partition user data from the data port and is further adapted to store within the second partition user data from the embedded block RAM.

Abstract: Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in one embodiment, a programmable logic device includes a plurality of logic blocks adapted to generate user data during operation of the programmable logic device; a plurality of registers adapted to store the user data during a reprogramming operation of the programmable logic device; and configurable routing resources adapted to provide a programmed data path between the logic blocks and the registers.

Abstract: In embodiment of the invention, a programmable logic device includes configuration memory adapted to be programmed with configuration data and a plurality of programmable fuses adapted to store a security key for use with configuration data. The security key includes a plurality of data bit values, wherein each data bit value of the security key is associated with a subset of a least three fuses each storing a bit. Each of a plurality of decoders is adapted to retrieve a data bit value of the security key by providing the bit value stored by a majority of the fuses of the associated subset as the data bit value of the security key.