Abstract: A method of determining a frame rate of a data frame in a communication system by using apriori knowledge of data frame. In one embodiment, a signal is received at the communication device. Then a data frame portion of the signal is isolated. Next, a potential frame rate is chosen and the data frame is formatted accordingly. Decoding, at the chosen potential frame rate, occurs on the data frame. Then, a tail bit portion of the data frame is isolated. Afterward, a logic level of the decoded tail bit data is compared against the apriori knowledge of a transmitted logic level for the tail bit portion of the data frame. In addition, comparisons are also made between other data metrics and their expected values. Finally, a level of confidence is communicated to the communication device based upon a result of the comparisons.

Abstract: An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate (S).